公开(公告)号：EP1587066B1

公开(公告)日：2009-04-08

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

公开(公告)号：EP1587066A3

公开(公告)日：2005-11-02

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 写入驱动器（510; 1210）通过互连（560; 1260）通过连接到写入头（570; 1270）的头来驱动写入电流（IL）。 写入驱动器（510; 1210）包括匹配互连（560; 1260）和升压电路（512; 1212）的奇特征阻抗的输出电阻的电路（514.556; 1214,1256; 1340）。 升压电路（512; 1212）连接在电源电压（VCC）和电压基准（VEE）之间，并且包括至少一个电流发生器（440,1140），例如MOS晶体管，连接到输入节点 （420; 1120）的电容器（422; 1122）。

公开(公告)号：EP1587066A2

公开(公告)日：2005-10-19

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 通过驱动连接到写头的头的写入电流（IL）（570; 1270）; A写入驱动器（1210 510）通过向间连接（560; 1260）。 写入驱动器（510; 1210）包括电路（514556; 1214.1256; 1340）输出电阻匹配到互连的奇数特性阻抗（560; 1260）和一个升压电路（512; 1212）。 升压电路（512; 1212）被连接在电源电压（VCC）和参考电压（VEE）之间，并且至少包括一个电流发生器（440.1140）：如一个MOS晶体管，连接到所述输入节点 （422; 1122）的单个电容器的（420; 1120）。

公开(公告)号：EP1310955A3

公开(公告)日：2007-02-21

申请号：EP02257758.9

申请日：2002-11-08

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Posat, Baris ,  Ozanoglu, Kemal ,  Alini, Roberto

IPC: G11B19/02 ,  G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit (100) includes switching circuitry (111,112,113,114,116,117,118,119) connected between the terminals (42A,42B) of the write head (42) and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry (125) that generates control signals for controlling the switching circuitry.

公开(公告)号：EP1585130A3

公开(公告)日：2005-12-14

申请号：EP05251685.3

申请日：2005-03-18

Applicant: STMicroelectronics, Inc.

Inventor： Ozanoglu, Kemal ,  Posat, Baris ,  Alini, Roberto

IPC: G11B20/22

CPC classification number: G11B20/10009 ,  G11B20/22 ,  G11B2005/0016

Abstract: A preamplifier for correcting for thermal asperity transients in disk drives using magneto resistive read heads. The preamplifier has an input gain stage receiving a signal from the read head and an output buffer outputting a reader output to a read channel that is filtered of thermal asperity transients by a high pass filter positioned between the input gain stage and the output buffer. The high pass filter is voltage controlled based on an input control signal from a filter controller. The filter controller uses a low pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.

Abstract translation: 前置放大器，用于校正使用磁阻读取磁头的磁盘驱动器中的热突起瞬变。 前置放大器具有从读取头接收信号的输入增益级以及将读取器输出输出到读取通道的输出缓冲器，所述读取通道由位于输入增益级和输出缓冲器之间的高通滤波器对热异常瞬态进行滤波。 高通滤波器是基于来自滤波器控制器的输入控制信号进行电压控制的。 滤波器控制器使用低通滤波器作为峰值检测器来检测高通滤波器输入或输出电压中的峰值。 基于低通滤波器输出的绝对值的递增函数，将低通滤波器输出应用于产生用于高通滤波器的控制信号的非线性函数发生器。

公开(公告)号：EP1310955A2

公开(公告)日：2003-05-14

申请号：EP02257758.9

申请日：2002-11-08

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Posat, Baris ,  Ozanoglu, Kemal ,  Alini, Roberto

IPC: G11B19/02 ,  G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit (100) includes switching circuitry (111,112,113,114,116,117,118,119) connected between the terminals (42A,42B) of the write head (42) and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry (125) that generates control signals for controlling the switching circuitry.

Abstract translation: 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳定状态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常在写入头中的稳态电流电平之间的转换期间向写入头提供不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路（100）包括连接在写入头（42）的端子（42A，42B）之间的开关电路（111,112,113,114,116,117,118,119）和诸如正和负电压源的参考电压源。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路（125）。

公开(公告)号：EP1441341A3

公开(公告)日：2008-11-05

申请号：EP04250285.6

申请日：2004-01-20

Applicant: STMicroelectronics, Inc.

Inventor： Posat, Baris ,  Ozanoglu, Kemal ,  Venca, Alessandro

IPC: G11B20/10 ,  G11B5/012 ,  G11B5/09 ,  H03F3/45

CPC classification number: G11B20/10009 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013 ,  G11B2005/0029 ,  H03F1/42 ,  H03F3/45278 ,  H03F2200/36 ,  H03F2200/432 ,  H03F2203/45318 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45648

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

Abstract translation: 公开了一种放大电路和方法，用于放大诸如由磁盘驱动器的读取头产生的电信号的电信号。 该电路包括一对交叉耦合的差分放大器电路。 每个差分放大器电路是不对称的，包括不同晶体管类型的两个输入晶体管 例如，每个差分放大器电路的两个输入晶体管中的第一个可以是双极晶体管，并且两个输入晶体管中的第二个可以是场效应晶体管。 通过使用非对称差分放大器电路，获得相对较宽的工作频率范围。

公开(公告)号：EP1585130A2

公开(公告)日：2005-10-12

申请号：EP05251685.3

申请日：2005-03-18

Applicant: STMicroelectronics, Inc.

Inventor： Ozanoglu, Kemal ,  Posat, Baris ,  Alini, Roberto

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B20/22 ,  G11B2005/0016

Abstract: A preamplifier for correcting for thermal asperity transients in disk drives using magneto resistive read heads. The preamplifier has an input gain stage receiving a signal from the read head and an output buffer outputting a reader output to a read channel that is filtered of thermal asperity transients by a high pass filter positioned between the input gain stage and the output buffer. The high pass filter is voltage controlled based on an input control signal from a filter controller. The filter controller uses a low pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.

Abstract translation: 一种前置放大器，用于使用磁阻读取头校正磁盘驱动器中的热凹凸瞬变。 前置放大器具有接收来自读取头的信号的输入增益级和输出缓冲器，该输出缓冲器通过位于输入增益级和输出缓冲器之间的高通滤波器将读出器输出输出输出到读取通道，该读取通道被过滤掉热不平坦瞬变。 高通滤波器基于来自滤波器控制器的输入控制信号进行电压控制。 滤波器控制器使用用作峰值检测器的低通滤波器来检测高通滤波器的输入或输出电压中的峰值。 低通滤波器输出被应用于基于低通滤波器输出的绝对值的增加函数产生高通滤波器的控制信号的非线性函数发生器。

公开(公告)号：EP1603120A1

公开(公告)日：2005-12-07

申请号：EP05252821.3

申请日：2005-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 写驱动器通过连接到写头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态，以产生具有一半负载电流幅度的脉冲电流。 该电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间内进入反向偏置。

公开(公告)号：EP1587067A3

公开(公告)日：2005-11-02

申请号：EP05252273.7

申请日：2005-04-12

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26 ,  H04L25/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.