公开(公告)号：EP1587066A3

公开(公告)日：2005-11-02

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 写入驱动器（510; 1210）通过互连（560; 1260）通过连接到写入头（570; 1270）的头来驱动写入电流（IL）。 写入驱动器（510; 1210）包括匹配互连（560; 1260）和升压电路（512; 1212）的奇特征阻抗的输出电阻的电路（514.556; 1214,1256; 1340）。 升压电路（512; 1212）连接在电源电压（VCC）和电压基准（VEE）之间，并且包括至少一个电流发生器（440,1140），例如MOS晶体管，连接到输入节点 （420; 1120）的电容器（422; 1122）。

公开(公告)号：EP1587066A2

公开(公告)日：2005-10-19

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver (510;1210) driving a write current (IL) through a head connected to the write head (570;1270) by an interconnect (560;1260). The write driver (510;1210) includes a circuit (514.556;1214,1256;1340) matching output resistance to the odd characteristic impedance of the interconnect (560;1260) and a voltage boosting circuit (512;1212). The voltage boosting circuit (512;1212) is connected between a supply voltage (VCC) and a voltage reference (VEE), and includes at least a current generator (440,1140), such as a MOS transistor, connected to the input node (422;1122) of a single capacitor (420;1120).

Abstract translation: 通过驱动连接到写头的头的写入电流（IL）（570; 1270）; A写入驱动器（1210 510）通过向间连接（560; 1260）。 写入驱动器（510; 1210）包括电路（514556; 1214.1256; 1340）输出电阻匹配到互连的奇数特性阻抗（560; 1260）和一个升压电路（512; 1212）。 升压电路（512; 1212）被连接在电源电压（VCC）和参考电压（VEE）之间，并且至少包括一个电流发生器（440.1140）：如一个MOS晶体管，连接到所述输入节点 （422; 1122）的单个电容器的（420; 1120）。

公开(公告)号：EP1587066B1

公开(公告)日：2009-04-08

申请号：EP05008158.7

申请日：2005-04-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

公开(公告)号：EP1130768A3

公开(公告)日：2003-09-17

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14 ,  H03F3/45

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

公开(公告)号：EP1130768A2

公开(公告)日：2001-09-05

申请号：EP01100815.8

申请日：2001-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Cazzaniga, Marco ,  Venca, Alessandro

IPC: H03D7/14

CPC classification number: G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells (10,11), each cell comprising a pair of bipolar transistors (2,3;6,7) with coupled emitters. A first transistor (2,6) of each cell (10,11) receives an input signal (Vin+,Vin-) on its base terminal and has its collector terminal coupled to a first voltage reference (Vcc) through a bias member (4,8). Advantageously, the second transistor (3,7) of each cell is a diode configuration, and the cells are interconnected at a common node (A) corresponding to the base terminals of the second transistors (3,7) in each pair.
This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract translation: 本发明涉及一种低电源模拟乘法器，其包括一对差分单元（10,11），每个单元包括具有耦合发射器的一对双极晶体管（2,3; 6,7）。 每个单元（10,11）的第一晶体管（2,6）在其基极上接收输入信号（Vin +，Vin-），并且其集电极通过偏置构件（4）耦合到第一参考电压（Vcc） ，8）。 有利地，每个单元的第二晶体管（3,7）是二极管配置，并且单元在对应于每对中的第二晶体管（3,7）的基极端子的公共节点（A）处互连。 这种乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及输出信号的减少的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。

公开(公告)号：EP1441341A3

公开(公告)日：2008-11-05

申请号：EP04250285.6

申请日：2004-01-20

Applicant: STMicroelectronics, Inc.

Inventor： Posat, Baris ,  Ozanoglu, Kemal ,  Venca, Alessandro

IPC: G11B20/10 ,  G11B5/012 ,  G11B5/09 ,  H03F3/45

CPC classification number: G11B20/10009 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013 ,  G11B2005/0029 ,  H03F1/42 ,  H03F3/45278 ,  H03F2200/36 ,  H03F2200/432 ,  H03F2203/45318 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45648

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

Abstract translation: 公开了一种放大电路和方法，用于放大诸如由磁盘驱动器的读取头产生的电信号的电信号。 该电路包括一对交叉耦合的差分放大器电路。 每个差分放大器电路是不对称的，包括不同晶体管类型的两个输入晶体管 例如，每个差分放大器电路的两个输入晶体管中的第一个可以是双极晶体管，并且两个输入晶体管中的第二个可以是场效应晶体管。 通过使用非对称差分放大器电路，获得相对较宽的工作频率范围。

公开(公告)号：EP1603120A1

公开(公告)日：2005-12-07

申请号：EP05252821.3

申请日：2005-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 写驱动器通过连接到写头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态，以产生具有一半负载电流幅度的脉冲电流。 该电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间内进入反向偏置。

公开(公告)号：EP1587067A3

公开(公告)日：2005-11-02

申请号：EP05252273.7

申请日：2005-04-12

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26 ,  H04L25/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

公开(公告)号：EP1587067A2

公开(公告)日：2005-10-19

申请号：EP05252273.7

申请日：2005-04-12

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract translation: 用于驱动写入电流的写入驱动器通过由互连或柔性传输线连接到写入头的写入头。 写入驱动器包括将写入驱动器的输出阻抗匹配到互连的奇特性阻抗的电路，并且包括产生到写入头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，该电压源用于在互连的传输延迟的两倍的初始时段期间在输出电阻器上保持零电压降。

公开(公告)号：EP1441341A2

公开(公告)日：2004-07-28

申请号：EP04250285.6

申请日：2004-01-20

Applicant: STMicroelectronics, Inc.

Inventor： Posat, Baris ,  Ozanoglu, Kemal ,  Venca, Alessandro

IPC: G11B20/00 ,  G11B5/00

CPC classification number: G11B20/10009 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013 ,  G11B2005/0029 ,  H03F1/42 ,  H03F3/45278 ,  H03F2200/36 ,  H03F2200/432 ,  H03F2203/45318 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45648

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.