公开(公告)号：EP1376413A1

公开(公告)日：2004-01-02

申请号：EP02425415.3

申请日：2002-06-25

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd.

Inventor： Blasi, Gianluca ,  Tayal, Reenee

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  Y10S707/99933

Abstract: A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language comprises a repository (10) storing a general set of self-checking tests applicable to the integrated circuits, means for entering behaviour data (21) of an integrated circuit model (20), means for entering configuration data (22) of the integrated circuit model and means for automatically generating test benches (30) in said Hardware Description Language, which means are configured to make a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behaviour data.

Abstract translation: 一种用于验证由硬件描述语言中的模型指定的集成电路的基于计算机的测试台发生器（1）包括存储适用于集成电路的一般的一组自检测试的存储库（10），用于输入行为数据（21）的装置 集成电路模型（20）的装置，用于输入集成电路模型的配置数据（22）的装置和用于在所述硬件描述语言中自动生成测试台（30）的装置，所述装置被配置为进行适当的选择和设置 根据指定的集成电路模型，配置和行为数据从存储库进行测试。

公开(公告)号：EP1638108B1

公开(公告)日：2008-07-23

申请号：EP04425692.3

申请日：2004-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Blasi, Gianluca ,  Vese, Barbara

IPC: G11C8/16

CPC classification number: G11C7/1075 ,  G11C8/16

公开(公告)号：EP1677309A2

公开(公告)日：2006-07-05

申请号：EP05425899.1

申请日：2005-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Blasi, Gianluca ,  Vese, Barbara

IPC: G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C7/12 ,  G11C7/22

Abstract: A memory device (100) comprises:

an array (MC, DMC) of memory cells (200, 300), each of which comprises word lines (WL0, WL1) and bit lines (BLL, BLR, BC, BT);
means for managing (CTRL, DGS, GS, WDEC, PREDEC, DLS, LS) array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines.

These managing means include a control block (CTRL) for generating a first enable signal (OUT) of the precharge step and a second enable signal (AWL) of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract translation: 一种存储器件（100），包括：存储单元（200,300）的阵列（MC，DMC），每个存储单元包括字线（WL0，WL1）和位线（BLL，BLR，BC，BT）; 用于管理通过执行预充电位线的步骤和开启字线的步骤来执行（CTRL，DGS，GS，WDEC，PREDEC，DLS，LS）阵列读取操作的装置。 这些管理装置包括用于产生预充电步骤的第一使能信号（OUT）和接通步骤的第二使能信号（AWL）的控制块（CTRL），使得在相同的读取操作中，预充电和接通 步骤部分并发。

公开(公告)号：EP1638108A1

公开(公告)日：2006-03-22

申请号：EP04425692.3

申请日：2004-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Blasi, Gianluca ,  Vese, Barbara

IPC: G11C8/16

CPC classification number: G11C7/1075 ,  G11C8/16

Abstract: A semi-conductor memory (100) comprises a memory device (CORE) to store digital data being provided with a first number of intermediate output ports including a first intermediate output port (QA).
Furthermore, the memory comprises register means (604) that can be selectively connected to said first intermediate output port (QA) to store data in the memory device and a second number of output ports (OP 1 -OP NR ) including first and second output ports.
In addition, the memory comprises an interface device (IF) destined to receive strobe signals (SQA) from said memory device, each being indicative of the presence of data on said at least one intermediate output port. This interface device (IF), based on said strobe signals (SQA), controls the register means (604) to provide the data stored in the register on the first and second output ports means, by emulating a multi-port memory where said second number is greater than said first number.

Abstract translation: 半导体存储器（100）包括存储设备（CORE），用于存储提供有包括第一中间输出端口（QA）的第一数量的中间输出端口的数字数据。 此外，存储器包括寄存器装置（604），其可以选择性地连接到所述第一中间输出端口（QA）以将数据存储在存储器件中，以及第二数量的输出端口（OP 1 -OP NR），包括第一和第二输出 端口。 另外，存储器包括一个接收装置（IF），该接口装置用于从所述存储装置接收选通信号（SQA），每一个指示在所述至少一个中间输出端口上存在数据。 该接口装置（IF）基于所述选通信号（SQA）控制寄存器装置（604），通过模拟多端口存储器来提供存储在第一和第二输出端口装置中的寄存器中的数据，其中所述第二 数字大于所述第一个数字。

公开(公告)号：EP1677309A3

公开(公告)日：2006-09-06

申请号：EP05425899.1

申请日：2005-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Blasi, Gianluca ,  Vese, Barbara

IPC: G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C7/12 ,  G11C7/22

Abstract: A memory device (100) comprises:

an array (MC, DMC) of memory cells (200, 300), each of which comprises word lines (WL0, WL1) and bit lines (BLL, BLR, BC, BT);
means for managing (CTRL, DGS, GS, WDEC, PREDEC, DLS, LS) array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines.

These managing means include a control block (CTRL) for generating a first enable signal (OUT) of the precharge step and a second enable signal (AWL) of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.