公开(公告)号：US10978340B2

公开(公告)日：2021-04-13

申请号：US16384147

申请日：2019-04-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L27/12 ,  H01L27/146 ,  H01L27/06 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/74 ,  H01L21/02

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US10535552B2

公开(公告)日：2020-01-14

申请号：US15892696

申请日：2018-02-09

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US20170103913A1

公开(公告)日：2017-04-13

申请号：US15129328

申请日：2015-03-27

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US20150364520A1

公开(公告)日：2015-12-17

申请号：US14738529

申请日：2015-06-12

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre

IPC: H01L27/146

CPC classification number: H01L31/02327 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689 ,  H01L31/0232 ,  H01L31/0352 ,  H01L31/042

Abstract: The disclosure relates to an image sensor comprising a substrate region in a semiconductor material; an active layer in contact with the substrate region; and a photodiode array formed in the active layer. The substrate region has a doping level such that the resistivity of the substrate region is less than 6 mOhm•cm.

Abstract translation: 本公开涉及一种包括半导体材料中的衬底区域的图像传感器; 与所述衬底区域接触的有源层; 以及形成在有源层中的光电二极管阵列。 衬底区域具有使得衬底区域的电阻率小于6mOhm·cm的掺杂水平。

公开(公告)号：US20180166318A1

公开(公告)日：2018-06-14

申请号：US15892696

申请日：2018-02-09

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US20160104729A1

公开(公告)日：2016-04-14

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Abstract translation: 一种制造钉扎光电二极管的方法，包括：在第二导电类型的衬底上形成光子转换到第一导电类型的电荷的区域; 用第二导电类型的重掺杂绝缘体层涂覆所述区域; 和退火以确保掺杂剂从重掺杂绝缘体层扩散。

公开(公告)号：US09312408B2

公开(公告)日：2016-04-12

申请号：US14738529

申请日：2015-06-12

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre

IPC: H01L31/0232 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/042

CPC classification number: H01L31/02327 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689 ,  H01L31/0232 ,  H01L31/0352 ,  H01L31/042

Abstract: The disclosure relates to an image sensor comprising a substrate region in a semiconductor material; an active layer in contact with the substrate region; and a photodiode array formed in the active layer. The substrate region has a doping level such that the resistivity of the substrate region is less than 6 mOhm·cm.

Abstract translation: 本公开涉及一种包括半导体材料中的衬底区域的图像传感器; 与所述衬底区域接触的有源层; 以及形成在有源层中的光电二极管阵列。 衬底区域具有使得衬底区域的电阻率小于6mOhm·cm的掺杂水平。

公开(公告)号：US20170294379A1

公开(公告)日：2017-10-12

申请号：US15093416

申请日：2016-04-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76877 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/0649

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US20170271392A1

公开(公告)日：2017-09-21

申请号：US15617748

申请日：2017-06-08

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre

IPC: H01L27/146 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L27/14629 ,  H01L21/7624 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689

Abstract: A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer.

公开(公告)号：US20170194498A1

公开(公告)日：2017-07-06

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.