公开(公告)号：US10367068B2

公开(公告)日：2019-07-30

申请号：US15427656

申请日：2017-02-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US09947650B1

公开(公告)日：2018-04-17

申请号：US15497993

申请日：2017-04-26

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US20180102358A1

公开(公告)日：2018-04-12

申请号：US15497993

申请日：2017-04-26

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US20180061833A1

公开(公告)日：2018-03-01

申请号：US15804669

申请日：2017-11-06

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L29/786 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78654

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US20170288059A1

公开(公告)日：2017-10-05

申请号：US15230699

申请日：2016-08-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/743 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78615

Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

公开(公告)号：US20170179196A1

公开(公告)日：2017-06-22

申请号：US15387850

申请日：2016-12-22

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Laurent GRENOUILLET ,  Sotirios Athanasiou ,  Philippe Galy

IPC: H01L27/24 ,  H01L27/12 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2454 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/53 ,  H01L27/101 ,  H01L27/1207 ,  H01L27/2436 ,  H01L28/00 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147

Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

公开(公告)号：US11380766B2

公开(公告)日：2022-07-05

申请号：US16434920

申请日：2019-06-07

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786 ,  H01L29/72 ,  H01L29/423 ,  H01L29/10 ,  H01L29/735

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US09831288B2

公开(公告)日：2017-11-28

申请号：US15387850

申请日：2016-12-22

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Laurent Grenouillet ,  Sotirios Athanasiou ,  Philippe Galy

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/12 ,  H01L45/00 ,  H01L27/10

CPC classification number: H01L27/2454 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/53 ,  H01L27/101 ,  H01L27/1207 ,  H01L27/2436 ,  H01L28/00 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147

Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

公开(公告)号：US09746863B2

公开(公告)日：2017-08-29

申请号：US14960052

申请日：2015-12-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou ,  Julien Le Coz ,  Sylvain Engels

IPC: H01L23/34 ,  G05F1/46 ,  H01L27/02 ,  H01L27/06

CPC classification number: G05F1/463 ,  H01L23/345 ,  H01L27/0251 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.

公开(公告)号：US20170012043A1

公开(公告)日：2017-01-12

申请号：US15041593

申请日：2016-02-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L21/84 ,  H01L23/528 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78654

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract translation: 使用第二MOS晶体管在绝缘体上的硅衬底的有源区中及其上产生用于第一MOS晶体管的衬底接触区，而没有任何PN结的也在激活区中提供。 第二MOS晶体管的源极或漏极区域中的至少一个上的接触焊盘形成衬底接触区域。