公开(公告)号：EP2515443A1

公开(公告)日：2012-10-24

申请号：EP11425112.7

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl ,  L'Université de Monastir

Inventor： Zid, Mounir ,  Scandurra, Alberto ,  Pistritto, Carmelo ,  Tourki, Rached

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: A data serializer comprising an input configured to receive a plurality of sets of parallel data, each set of data comprising n bits and at least one serializing stage configured to receive a set of n bits of parallel data and to convert said parallel data to a serial stream of data, said at least one serializing stage comprising a chain of flip flops each of which is arranged to selectively receive one of a bit of data and data output from a preceding flip flop, an output of a last flip flop of said chain of flip flops providing said serial stream of data.

Abstract translation: 一种数据串行化器，包括被配置为接收多组并行数据的输入，每组数据包括n位，并且至少一个串行化级被配置为接收一组n位并行数据并将所述并行数据转换为串行 数据流，所述至少一个串行化级包括一串触发器，每一个触发器被安排为选择性地接收从前一个触发器输出的一位数据和数据中的一个，所述链的最后一个触发器的输出 提供所述串行数据流的触发器。

公开(公告)号：EP2515442A1

公开(公告)日：2012-10-24

申请号：EP11425111.9

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl ,  L'Université de Monastir

Inventor： Zid, Mounir ,  Scandurra, Alberto ,  Pistritto, Carmelo ,  Tourki, Rached

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: An arrangement comprises an input configured to receive data; and at least one multiplexer configured to receive a first logic level at a first input and a second logic level at a second level, at least a part of said data being received at a control input of said multiplexer.

Abstract translation: 一种配置包括被配置为接收数据的输入; 以及至少一个多路复用器，被配置为在第一输入端接收第一逻辑电平并且在第二电平接收第二逻辑电平，所述数据的至少一部分在所述多路复用器的控制输入端被接收。

公开(公告)号：EP2515226A1

公开(公告)日：2012-10-24

申请号：EP11425113.5

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl

Inventor： Zid, Mounir ,  Scandurra, Alberto

IPC: G06F5/08

CPC classification number: G06F5/08

Abstract: An arrangement comprising a plurality of data stores, each data store being configured to store data, and a controller arranged to selectively apply a clock signal to said respective data stores.

Abstract translation: 一种包括多个数据存储器的装置，每个数据存储器被配置为存储数据，以及控制器，被布置为选择性地将时钟信号应用于所述各个数据存储器。

公开(公告)号：EP2515197A1

公开(公告)日：2012-10-24

申请号：EP11425114.3

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl

Inventor： Zid, Mounir ,  Scandurra, Alberto

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: A circuit comprises a first Muller gate having a first input configured to receive a clock signal, a second input configured to receive an enable signal and an output. A logic circuit is also provided having a first input configured to receive said clock signal, and a second input configured to receive an input dependent on said output, said logic circuit being configured to provide a gated clock output.

Abstract translation: 电路包括具有被配置为接收时钟信号的第一输入的第一穆勒门，被配置为接收使能信号和输出的第二输入。 还提供了具有被配置为接收所述时钟信号的第一输入的逻辑电路，以及被配置为接收依赖于所述输出的输入的第二输入，所述逻辑电路被配置为提供门控时钟输出。