公开(公告)号：EP2075710B1

公开(公告)日：2012-12-05

申请号：EP08022447.0

申请日：2008-12-24

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/42 ,  H04L7/00

CPC classification number: H04L7/10 ,  H04L7/0037

公开(公告)号：EP1763078B1

公开(公告)日：2013-04-10

申请号：EP05019639.3

申请日：2005-09-09

Applicant: STMicroelectronics Srl

Inventor： Canegallo, Roberto ,  Mirandola, Mario ,  Fazzi, Alberto ,  Magagni, Luca ,  Guerrieri Roberto

IPC: H01L25/065

CPC classification number: G01R31/2891 ,  G01R31/312 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP1762943B1

公开(公告)日：2014-07-09

申请号：EP05019644.3

申请日：2005-09-09

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Magagni, Luca ,  Fazzi, Alberto ,  Canegallo, Roberto ,  Guerrieri, Roberto

IPC: H01L25/065 ,  G06F13/40

CPC classification number: H01L25/0657 ,  G06F13/4077 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP2075708B1

公开(公告)日：2013-02-13

申请号：EP08022446.2

申请日：2008-12-24

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/40 ,  H04L7/00

CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

公开(公告)号：EP2075708A3

公开(公告)日：2010-05-12

申请号：EP08022446.2

申请日：2008-12-24

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/40 ,  H04L7/00

CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

Abstract: The invention relates to a communication system for the connection between timing non correlated synchronous devices of the type comprising at least one transmitter (30) and one receiver (40) inserted between a first and a second voltage reference (Vcc, GND) and connected to each other by means of a capacitive or resistive channel (25) in correspondence with respective transmitting (TX) and receiving (RX) terminals. Advantageously according to the invention, the receiver (40) comprises at least one synchronous input stage (41) suitable for receiving on said receiving terminal (RX) a datum (D) and associated with a synchronous output stage (42) suitable for transmitting said datum (D) in a synchronised way with a clock signal (CP) on a synchronised receiving terminal (RXs).

公开(公告)号：EP2341626B1

公开(公告)日：2015-08-26

申请号：EP10197444.2

申请日：2010-12-30

Applicant: STMicroelectronics Srl

Inventor： Canegallo, Roberto ,  Cardu, Roberto ,  Scandiuzzo, Mauro ,  Cani, Salvatore Valerio ,  Perugini, Luca

IPC: H03K19/0175 ,  G01R31/312

CPC classification number: H03K19/0175 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2924/01021 ,  H01L2924/13091

公开(公告)号：EP2075710A3

公开(公告)日：2010-05-05

申请号：EP08022447.0

申请日：2008-12-24

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/42 ,  H04L7/00

CPC classification number: H04L7/10 ,  H04L7/0037

Abstract: The invention relates to a communication system between a first and a second independently clocked devices (L,R), in particular chips, comprising, for each device, at least a transmitter (TXL,TXR) and a receiver (RXL,RXR) connected to each other in a crossed way in correspondence of an inter-chip communication channel (ICC). Advantageously according to the invention, the communication system further comprises a synchronizer (40) in turn including at least a first and a second synchronization block (20L,20R), having respective input terminals (INrL,INrR) connected to the receivers (RXL,RXR) and respective output terminals (OUTtL,OUTtR) connected to the transmitters (TXL,TXR) and comprising at least:
- a test pattern generator (23);
- comparison means (21,22) to check a matching between stored and received test pattern signals; and
- a delay block (26) able to change the clock phases.