公开(公告)号：EP1873648B1

公开(公告)日：2010-08-18

申请号：EP06116248.3

申请日：2006-06-28

Applicant: STMicroelectronics Srl ,  STMicroelectronics N.V.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe ,  Salurso, Elena ,  Guidetti, Elio

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

Abstract: A data cache memory coupled to a processor architecture including a plurality of processor clusters (Cluster0,..., Cluster3) is adapted to operate simultaneously on scalar and vectorial data by providing in the data cache memory data locations for storing therein data for processing by the architecture, and accessing the data locations in the data cache memory either in a scalar mode or in a vectorial mode. This is done preferably by explicitly mapping those locations of the cache memory considered as scalar and those locations of the cache memory considered as vectorial.

公开(公告)号：EP1416720B1

公开(公告)日：2012-05-09

申请号：EP02425655.4

申请日：2002-10-29

Applicant: STMicroelectronics Srl

Inventor： Pappalardo, Francesco ,  Capra, Alessandro ,  Mancuso, Massimo ,  Broquin, Hervé ,  Foderà, Paolo Antonino ,  Salurso, Elena

IPC: H04N1/64

CPC classification number: H04N1/648