公开(公告)号：EP1845660B1

公开(公告)日：2012-08-29

申请号：EP06425259.6

申请日：2006-04-12

Applicant: STMicroelectronics Srl

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: H04L12/28

CPC classification number: H04L12/2856

公开(公告)号：EP1873648B1

公开(公告)日：2010-08-18

申请号：EP06116248.3

申请日：2006-06-28

Applicant: STMicroelectronics Srl ,  STMicroelectronics N.V.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe ,  Salurso, Elena ,  Guidetti, Elio

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

Abstract: A data cache memory coupled to a processor architecture including a plurality of processor clusters (Cluster0,..., Cluster3) is adapted to operate simultaneously on scalar and vectorial data by providing in the data cache memory data locations for storing therein data for processing by the architecture, and accessing the data locations in the data cache memory either in a scalar mode or in a vectorial mode. This is done preferably by explicitly mapping those locations of the cache memory considered as scalar and those locations of the cache memory considered as vectorial.

公开(公告)号：EP1416720B1

公开(公告)日：2012-05-09

申请号：EP02425655.4

申请日：2002-10-29

Applicant: STMicroelectronics Srl

Inventor： Pappalardo, Francesco ,  Capra, Alessandro ,  Mancuso, Massimo ,  Broquin, Hervé ,  Foderà, Paolo Antonino ,  Salurso, Elena

IPC: H04N1/64

CPC classification number: H04N1/648

公开(公告)号：EP1717753A3

公开(公告)日：2010-06-02

申请号：EP06112972.2

申请日：2006-04-24

Applicant: STMicroelectronics Srl

Inventor： Spampinato, Giuseppe ,  Capra, Alessandro ,  Pappalardo, Francesco

IPC: G06T1/60

CPC classification number: G06T1/60

Abstract: An image generating pipeline (IGP) includes a digital signal processor for implementing processing blocks connected in cascade for processing an input image that includes an array of raw pixel values to generate a color image that includes an array of reconstructed pixel values. A memory is coupled to the digital signal processor for storing the raw pixel values and the array of reconstructed pixel values. The digital signal processor includes a data cache, and the raw pixel values of the input image are processed through the processing blocks in sub-arrays having fractional dimensions of the pixel dimensions of the whole image array. The sub-arrays include an input sub-array of pixel values being loaded from the memory for defining a working window. The sub-arrays of raw pixel values have a row-wise dimension of at least a fraction of a full row of the input image, and a column-wise dimension equal to or larger than a column-wise filtering action of a respective processing block to which the input sub-array is input. The digital signal processor outputs at least one fraction of full rows of completely reconstructed pixel values of the input image for storing in the memory.

公开(公告)号：EP1717708B1

公开(公告)日：2010-09-01

申请号：EP05103593.9

申请日：2005-04-29

Applicant: STMicroelectronics Srl

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

Abstract: A cache memory system (115), comprising at least one cache memory (205) and a cache memory controller (210, Ft, Fd, 225, 230, 235, 245, 252). The at least one cache memory includes a plurality of storage locations (RLj), each one identified by a corresponding cache address (CADDR) and being adapted to store tag address portions (TAGi) and data words (DATi), each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address (ADD) and to access the at least one cache memory based on the received first address.The cache memory controller includes a first address transformer (Ft, 225) adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations. The cache memory controller includes a hit detector (245) adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part (TAGp) of the first address, and a second address transformer (Fd, 225) adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function. The cache memory controller is further adapted to use the at least one second cache address for accessing the at least one cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.