公开(公告)号：EP1845660B1

公开(公告)日：2012-08-29

申请号：EP06425259.6

申请日：2006-04-12

Applicant: STMicroelectronics Srl

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: H04L12/28

CPC classification number: H04L12/2856

公开(公告)号：EP1717708B1

公开(公告)日：2010-09-01

申请号：EP05103593.9

申请日：2005-04-29

Applicant: STMicroelectronics Srl

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

Abstract: A cache memory system (115), comprising at least one cache memory (205) and a cache memory controller (210, Ft, Fd, 225, 230, 235, 245, 252). The at least one cache memory includes a plurality of storage locations (RLj), each one identified by a corresponding cache address (CADDR) and being adapted to store tag address portions (TAGi) and data words (DATi), each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address (ADD) and to access the at least one cache memory based on the received first address.The cache memory controller includes a first address transformer (Ft, 225) adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations. The cache memory controller includes a hit detector (245) adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part (TAGp) of the first address, and a second address transformer (Fd, 225) adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function. The cache memory controller is further adapted to use the at least one second cache address for accessing the at least one cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.