公开(公告)号：EP2015505A3

公开(公告)日：2016-11-16

申请号：EP08012447.2

申请日：2008-07-10

Applicant: STMicroelectronics Srl ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido Marco ,  Owen, Jefferson Eugene

IPC: H04L9/06 ,  G09C1/00

CPC classification number: H04L9/0637 ,  G09C1/00 ,  H04L2209/122 ,  H04L2209/125

Abstract: An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.

公开(公告)号：EP0827348A3

公开(公告)日：2001-03-07

申请号：EP97306447.0

申请日：1997-08-22

Applicant: STMicroelectronics, Inc.

Inventor： Diaz, Raul Zegers ,  Owen, Jefferson Eugene

IPC: H04N7/50 ,  G06F13/362

CPC classification number: H04N19/423 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4435

Abstract: An electronic system that contains a first device that requires a memory interface and video and/or audio decompression and/or compression device that shares a memory interface and memory with the first device while still permitting the video and/or audio decompression and/or compression device to operate in real time is disclosed.

公开(公告)号：EP0847204A3

公开(公告)日：2000-03-01

申请号：EP97309487.3

申请日：1997-11-25

Applicant: STMicroelectronics, Inc.

Inventor： Diaz, Raul Zegers ,  Balakrishnan, Jeyendran ,  Owen, Jefferson Eugene

IPC: H04N7/50

CPC classification number: H04N19/42 ,  H04N19/61

Abstract: Circuits and methods for subdividing a decoder into functional blocks that can be accessed separately. The decoder includes a decoder module having a parser, a block decoder and a motion compensation engine, which can all be further subdivided into functional blocks. The functional blocks can be bypassed in decompressing frames where the blocks are not necessary, or when the compression algorithm does not require the functional block, increasing the speed of the decoder. The functional blocks can also be reused for decompression or compression based on different standards, or for different operation in the decoder, such as decompression and compression. The decoder can be coupled to a processor and some of the functional block performed in the decoder's hardware and some are performed in the processor. In one embodiment of the invention and the processor determines which block are to be by-passed completely and which block are to be performed in software based on the decompression protocol to which the compressed frame is encoded to comply to, the capacity and speed of the processor, and the available memory. In another embodiment multiplexers can be added to the decoder to connect functional blocks so they can be by-passed or reused based on preprogramming of the multiplexers based on the decompression protocol to which the compressed frame is encoded to comply to, the capacity and speed of the processor, and the available memory.

Abstract translation: 用于将解码器细分为可单独访问的功能块的电路和方法。 解码器包括具有语法分析器，块解码器和运动补偿引擎的解码器模块，其可以进一步细分为功能块。 可以在对块不需要的帧进行解压缩时，或者当压缩算法不需要功能块时，可以绕过功能块，从而提高解码器的速度。 这些功能块还可以用于基于不同标准的解压缩或压缩，或解码器中的不同操作，例如解压缩和压缩。 解码器可以耦合到处理器，并且一些功能块在解码器的硬件中执行并且一些在处理器中执行。 在本发明的一个实施例中，处理器基于压缩帧被编码为符合的解压缩协议来确定哪个块将被完全旁路以及哪个块将在软件中被执行，因此，处理器的容量和速度 处理器和可用内存。 在另一个实施例中，可以将多路复用器添加到解码器以连接功能块，使得它们可以基于对多路复用器的预编程被绕过或重新使用，这基于压缩帧被编码为符合的解压缩协议， 处理器和可用内存。

公开(公告)号：EP2288168A3

公开(公告)日：2011-03-09

申请号：EP10176611.1

申请日：1997-08-22

Applicant: STMicroelectronics, Inc.

Inventor： Diaz, Raul Zegers ,  Owen, Jefferson Eugene

IPC: H04N7/50 ,  G06F13/362

CPC classification number: H04N19/423 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4435

Abstract: An electronic system coupled to a memory, comprising: a core logic chipset having access to the memory; a decoder having access to the memory; a memory interface coupled to the core logic chipset and the decoder, the memory interface having an arbiter coupled to a core logic chipset direct memory access engine and a decoder direct memory access engine, the arbiter for selectively providing access for the core logic chipset and the decoder to the memory; and a bus coupled to the memory, the first device and the decoder, wherein the decoder and the core logic chipset are coupled to the memory through the bus, the bus having a bandwidth providing access to the memory sufficient to maintain real-time operation of the decoder and to allow the core logic chipset to access the memory thereby enabling the decoder and the core logic chipset to share the memory; wherein said memory interface is operable to provide memory access to the core logic chipset through said bus when the decoder is not operating.

公开(公告)号：EP1715696A2

公开(公告)日：2006-10-25

申请号：EP06076530.2

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/50 ,  H04N7/26

Abstract: A digital video decoder comprising a bit unpacker that utilizes at least an encoded video data stream to produce a prediction data stream and a coding data stream; a motion compensation instruction encoder communicably coupled to the bit unpacker, the motion compensation instruction encoder utilizing at least the prediction data stream to selectively produce a set of motion compensation instructions; and a block decoder communicably coupled to the bit unpacker, the block decoder utilizing at least the coding data stream to produce a set of error terms.

Abstract translation: 一种数字视频解码器，包括利用至少编码视频数据流产生预测数据流和编码数据流的比特解包器; 运动补偿指令编码器，其可通信地耦合到所述位解码器，所述运动补偿指令编码器至少利用所述预测数据流选择性地产生一组运动补偿指令; 以及块解码器，其可通信地耦合到所述位解包器，所述块解码器至少利用所述编码数据流来产生一组误差项。

公开(公告)号：EP1009162A3

公开(公告)日：2005-08-17

申请号：EP99309801.1

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N5/00

CPC classification number: H04N19/44 ,  G11B20/10 ,  G11B27/105 ,  G11B2220/2562 ,  H04N21/40

Abstract: The present invention provides a system and an apparatus for a digital audio/video decoder comprising a file reader capable of obtaining an encoded audio/video data stream from a data source, a navigator that instructs the file reader to obtain the encoded audio/video data stream, a splitter that separates the encoded audio/video data stream obtained by the file reader into one or more component data streams, and a reprogrammable proxy filter that decodes and converts the one or more component data streams into three or more renderable signals including at least one renderable audio signal and at least two renderable video signals.

公开(公告)号：EP2288168A2

公开(公告)日：2011-02-23

申请号：EP10176611.1

申请日：1997-08-22

Applicant: STMicroelectronics, Inc.

Inventor： Diaz, Raul Zegers ,  Owen, Jefferson Eugene

IPC: H04N7/50

CPC classification number: H04N19/423 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4435

Abstract: An electronic system coupled to a memory, comprising: a core logic chipset having access to the memory; a decoder having access to the memory; a memory interface coupled to the core logic chipset and the decoder, the memory interface having an arbiter coupled to a core logic chipset direct memory access engine and a decoder direct memory access engine, the arbiter for selectively providing access for the core logic chipset and the decoder to the memory; and a bus coupled to the memory, the first device and the decoder, wherein the decoder and the core logic chipset are coupled to the memory through the bus, the bus having a bandwidth providing access to the memory sufficient to maintain real-time operation of the decoder and to allow the core logic chipset to access the memory thereby enabling the decoder and the core logic chipset to share the memory; wherein said memory interface is operable to provide memory access to the core logic chipset through said bus when the decoder is not operating.

Abstract translation: 一种耦合到存储器的电子系统，包括：具有访问所述存储器的核心逻辑芯片组; 解码器，其具有访问存储器的解码器; 存储器接口，其耦合到所述核心逻辑芯片组和所述解码器，所述存储器接口具有耦合到核心逻辑芯片组直接存储器存取引擎和解码器直接存储器访问引擎的仲裁器，所述仲裁器用于选择性地提供核心逻辑芯片组和 解码器到存储器; 以及耦合到存储器，第一器件和解码器的总线，其中解码器和核心逻辑芯片组通过总线耦合到存储器，总线具有提供对存储器的访问，足以维持实时操作 并且允许核心逻辑芯片组访问存储器，从而使得解码器和核心逻辑芯片组能够共享存储器; 其中当解码器不工作时，所述存储器接口可操作以通过所述总线提供对核心逻辑芯片组的存储器访问。

公开(公告)号：EP0847203B1

公开(公告)日：2006-05-24

申请号：EP97309486.5

申请日：1997-11-25

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  Balakrishnan, Jeyendran

IPC: H04N7/50

CPC classification number: H04N19/428 ,  H04N19/423 ,  H04N19/61

公开(公告)号：EP1009170A3

公开(公告)日：2004-04-14

申请号：EP99309802.9

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N7/36

CPC classification number: H04N19/43 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: The present invention provides a system, method and an apparatus for a digital video decoder, which includes a data processor that utilizes at least an encoded video data stream to produce one or more output streams. The one or more output streams includes at least a set of motion compensation instructions.

公开(公告)号：EP1009169A3

公开(公告)日：2002-03-06

申请号：EP99309800.3

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/36 ,  H04N7/50

CPC classification number: H04N19/523

Abstract: The present invention provides a system, method and an apparatus for a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.