公开(公告)号：EP1845442B1

公开(公告)日：2011-11-09

申请号：EP06112507.6

申请日：2006-04-11

Applicant: STMicroelectronics Srl ,  STMicroelectronics Limited

Inventor： Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Marsh, Andrew ,  Pelosi, Gerardo ,  Ravasio, Moris

IPC: G06F7/72

CPC classification number: G06F7/728 ,  G06F7/722

公开(公告)号：EP1845442A1

公开(公告)日：2007-10-17

申请号：EP06112507.6

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Limited

Inventor： Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Marsh, Andrew ,  Pelosi, Gerardo ,  Ravasio, Moris

IPC: G06F7/72

CPC classification number: G06F7/728 ,  G06F7/722

Abstract: The invention concerns a computing method performed by an electronic circuit and an electronic circuit for computing a modular operation with at least one operand (R) having a binary representation, at least comprising iteratively for each bit of this operand: doubling (33) the value of an intermediate result (Z) stored in a first memory element by shifting the bits of the intermediate result towards the most significant bit; and while (34) the most significant bit of the intermediate result is one, updating this intermediate result by subtracting the modulus (n) stored in a second memory element.

Abstract translation: 本发明涉及一种由电子电路和电子电路执行的计算方法，该电子电路用至少一个具有二进制表示的操作数（R）来计算模块化操作，至少包括对该操作数的每一位进行迭代：将该值加倍（33） 通过将中间结果的位移向最高有效位来存储在第一存储元件中的中间结果（Z）; 而当（34）中间结果的最高有效位为1时，通过减去存储在第二存储元件中的模数（n）来更新该中间结果。