公开(公告)号：EP1845442B1

公开(公告)日：2011-11-09

申请号：EP06112507.6

申请日：2006-04-11

Applicant: STMicroelectronics Srl ,  STMicroelectronics Limited

Inventor： Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Marsh, Andrew ,  Pelosi, Gerardo ,  Ravasio, Moris

IPC: G06F7/72

CPC classification number: G06F7/728 ,  G06F7/722

公开(公告)号：EP1675299B1

公开(公告)日：2018-08-01

申请号：EP05103298.5

申请日：2005-04-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  STMicroelectronics Srl

Inventor： Chen, Liqun ,  Harrison, Keith ,  Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Pelosi, Gerardo

IPC: H04L9/32

CPC classification number: H04L9/08 ,  H04L9/3073 ,  H04L9/321 ,  H04L2209/80 ,  H04W12/06

Abstract: Cryptographic methods are known that involve the computation of a non-degenerate bilinear mapping of first and second elements (P 1 , Q 1 ) one of which comprises a secret of a first entity (A). For a mapping implemented as, for example, a Tate pairing, the mapping is computable by applying a predetermined function (f) to the first and second elements (P 1 , Q 1 ) and then exponentiating the result with a known exponent (e pub ). Improvements in respect of computational loading, size of output, and security are enabled for the first party (A) by arranging for the first entity to carry out (12) only part of the mapping, a second entity (B) being used to complete computation (13) of the mapping. Cryptographic applications using these improvements are also disclosed.

公开(公告)号：EP2202911A1

公开(公告)日：2010-06-30

申请号：EP09178947.9

申请日：2009-12-11

Applicant: STMicroelectronics Srl

Inventor： Bertoni, Guido Marco

IPC: H04L9/08

CPC classification number: H04L9/0625 ,  H04L9/0631 ,  H04L9/0866

Abstract: A method (200) for transmitting a message between a first electronic device (C) and a second electronic device (MS i ) is described, comprising steps of:
- implementing an encryption algorithm, generating (202), by the first electronic device (C), a first data encryption key (K i ) identifying the second electronic device (MS i ) on the basis of a main data encryption key (MK) and an identification code (ID i ) of the second electronic device (MS i );
- implementing said encryption algorithm, generating (203), by the first electronic device (C) and the second electronic device (MS i ), a communication key (K di ) on the basis of said first data encryption key (K i ) and a reference datum (DT).

Abstract translation: 一种用于发送消息的第一电子设备（C），并且所述的第二电子装置（MSⅰ）之间，包括以下步骤的方法（200）： - 实现一种加密算法，生成（202），通过所述第一电子设备（ 第二电子设备的C），第一数据加密密钥（K I）确定第二电子装置（MS i）主数据加密密钥的（MK）的基础上，对识别码（IDⅰ）（MSⅰ） ; - 实施所述加密算法，生成（203），由所述第一电子装置（C）和所述第一数据加密密钥的基础上的第二电子设备（MS i）中，通信密钥（K二）（K i）和 参考日期（DT）。

公开(公告)号：EP2523385B1

公开(公告)日：2017-07-12

申请号：EP11164951.3

申请日：2011-05-05

Applicant: Proton World International N.V. ,  STMicroelectronics Srl

Inventor： Van Assche, Gilles ,  Daemen, Joan ,  Bertoni, Guido Marco

IPC: H04L9/00

CPC classification number: H04L9/002 ,  H04L9/004 ,  H04L9/06 ,  H04L2209/12

公开(公告)号：EP2015505A3

公开(公告)日：2016-11-16

申请号：EP08012447.2

申请日：2008-07-10

Applicant: STMicroelectronics Srl ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido Marco ,  Owen, Jefferson Eugene

IPC: H04L9/06 ,  G09C1/00

CPC classification number: H04L9/0637 ,  G09C1/00 ,  H04L2209/122 ,  H04L2209/125

Abstract: An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.

公开(公告)号：EP2523385A1

公开(公告)日：2012-11-14

申请号：EP11164951.3

申请日：2011-05-05

Applicant: PROTON WORLD INTERNATIONAL N.V. ,  STMicroelectronics Srl

Inventor： Van Assche, Gilles ,  Daemen, Joan ,  Bertoni, Guido Marco

IPC: H04L9/06

CPC classification number: H04L9/002 ,  H04L9/004 ,  H04L9/06 ,  H04L2209/12

Abstract: The invention concerns a method of performing a cryptographic operation comprising: receiving a plurality of binary input values (P 0 ...P N ); splitting said binary input values into a plurality of non-binary digits (P 0 '...P M ') of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block (306) on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit (Z 0 '...Z M ') of base r.

Abstract translation: 本发明涉及一种执行密码操作的方法，包括：接收多个二进制输入值（P 0 ... P N）; 将所述二进制输入值分解为基本r的多个非二进制数字（P 0'... P M'），其中r是大于2且不等于2的幂的整数; 并且通过在所述多个非二进制数字中的每一个上的密码块（306）执行不同的模r操作以生成基本r的至少一个输出数字（Z 0'... Z M'）。

公开(公告)号：EP1845442A1

公开(公告)日：2007-10-17

申请号：EP06112507.6

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Limited

Inventor： Bertoni, Guido Marco ,  Fragneto, Pasqualina ,  Marsh, Andrew ,  Pelosi, Gerardo ,  Ravasio, Moris

IPC: G06F7/72

CPC classification number: G06F7/728 ,  G06F7/722

Abstract: The invention concerns a computing method performed by an electronic circuit and an electronic circuit for computing a modular operation with at least one operand (R) having a binary representation, at least comprising iteratively for each bit of this operand: doubling (33) the value of an intermediate result (Z) stored in a first memory element by shifting the bits of the intermediate result towards the most significant bit; and while (34) the most significant bit of the intermediate result is one, updating this intermediate result by subtracting the modulus (n) stored in a second memory element.

Abstract translation: 本发明涉及一种由电子电路和电子电路执行的计算方法，该电子电路用至少一个具有二进制表示的操作数（R）来计算模块化操作，至少包括对该操作数的每一位进行迭代：将该值加倍（33） 通过将中间结果的位移向最高有效位来存储在第一存储元件中的中间结果（Z）; 而当（34）中间结果的最高有效位为1时，通过减去存储在第二存储元件中的模数（n）来更新该中间结果。