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1.发明授权
公开(公告)号：EP2348634B1
公开(公告)日：2014-03-19
申请号：EP10197058.0
申请日：2010-12-27
Applicant: STMicroelectronics Srl , STMicroelectronics Pvt. Ltd.
Inventor： Veggetti, Andrea Mario , Jain, Abhishek , Rohilla, Pankaj
CPC classification number: H03K3/012 , H03K3/0375 , H03K3/356008 , H03K19/0016
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公开(公告)号：EP2830221A1
公开(公告)日：2015-01-28
申请号：EP14190037.3
申请日：2007-12-28
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： Jain, Abhishek
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356156
Abstract: The present invention provides a flip flop circuit utilizing low power dissipation. The low power flip-flop circuit 300 includes a sensing circuit 304, a clock generating circuit 306, and an output sensing circuit. The flip flop is positive edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop output. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall depending on an external clock signal. In very large scale integration (VLSI) applications the data activity is generally of the order of 2-10 % of clock activity, so, the switching current which flows between a power supply to a ground terminal, when the data is constant and clock is toggling leads to high power dissipation and electromagnetic emissions (which has now become a serious problem in VLSI digital designs).
Abstract translation: 本发明提供一种利用低功耗的触发器电路。 低功率触发器电路300包括感测电路304，时钟发生电路306和输出感测电路。 触发器为正边沿触发，并在内部产生的伪时钟信号上工作。 感测电路检测输入信号和触发器输出的输出信号的变化。 时钟发生电路根据外部时钟信号产生急剧上升和下降的伪时钟信号。 在超大规模集成（VLSI）应用中，数据活动通常是时钟活动的2-10％的量级，所以当数据为恒定的时候，在接地端子的电源之间流动的开关电流，时钟为 切换导致高功率耗散和电磁辐射（现在已成为VLSI数字设计中的严重问题）。
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Patent Agency Ranking
公开(公告)号：EP1940027B1
公开(公告)日：2014-11-19
申请号：EP07150459.1
申请日：2007-12-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Jain, Abhishek
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356156
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公开(公告)号：EP1940027A3
公开(公告)日：2010-04-14
申请号：EP07150459.1
申请日：2007-12-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Jain, Abhishek
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356156
Abstract: The present invention provides a flip flop circuit (300) utilizing low power dissipation. The low power flip-flop circuit includes a flip-flop circuit (302), a clock generating circuit(306), and a sensing circuit (304). The flip flop is positive edge triggered and operates on an internally generated pseudo clock signal (CP). The sensing circuit senses a change in an input signal and an output signal of the flip-flop output. The clock generating circuit generates a pseudo clock signal (CP) with a sharp rise and fall depending on an external clock signal. In very large scale integration (VLSI) applications the data activity is generally of the order of 2-10 % of clock activity, so, the switching current which flows between a power supply to a ground terminal, when the data is constant and clock is toggling leads to high power dissipation and electromagnetic emissions (which has now become a serious problem in VLSI digital designs).
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公开(公告)号：EP1940027A2
公开(公告)日：2008-07-02
申请号：EP07150459.1
申请日：2007-12-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Jain, Abhishek
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356156
Abstract: The present invention provides a flip flop circuit (300) utilizing low power dissipation. The low power flip-flop circuit includes a flip-flop circuit (302), a clock generating circuit(306), and a sensing circuit (304). The flip flop is positive edge triggered and operates on an internally generated pseudo clock signal (CP). The sensing circuit senses a change in an input signal and an output signal of the flip-flop output. The clock generating circuit generates a pseudo clock signal (CP) with a sharp rise and fall depending on an external clock signal. In very large scale integration (VLSI) applications the data activity is generally of the order of 2-10 % of clock activity, so, the switching current which flows between a power supply to a ground terminal, when the data is constant and clock is toggling leads to high power dissipation and electromagnetic emissions (which has now become a serious problem in VLSI digital designs).
Abstract translation: 本发明提供一种利用低功耗的触发电路（300）。 低功率触发电路包括触发电路（302），时钟发生电路（306）和感测电路（304）。 触发器为正边沿触发，并在内部产生的伪时钟信号（CP）上工作。 感测电路检测输入信号和触发器输出的输出信号的变化。 时钟发生电路根据外部时钟信号产生急剧上升和下降的伪时钟信号（CP）。 在超大规模集成（VLSI）应用中，数据活动通常是时钟活动的2-10％的量级，所以当数据为恒定的时候，在接地端子的电源之间流动的开关电流， 切换导致高功率耗散和电磁辐射（现在已成为VLSI数字设计中的严重问题）。
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公开(公告)号：EP2830221B1
公开(公告)日：2017-02-08
申请号：EP14190037.3
申请日：2007-12-28
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： Jain, Abhishek
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356156
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7.发明公开
公开(公告)号：EP2348634A1
公开(公告)日：2011-07-27
申请号：EP10197058.0
申请日：2010-12-27
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Pvt. Ltd.
Inventor： Veggetti, Andrea Mario , Jain, Abhishek , Rohilla, Pankaj
CPC classification number: H03K3/012 , H03K3/0375 , H03K3/356008 , H03K19/0016
Abstract: The present invention relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop (10) and at least one retention cell (20; 200) connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal (SO), while during low consumption operation of the flip-flop circuit a latch circuit (22; 220) of the retention cell suitable to memorise data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
Abstract translation: 本发明涉及具有数据保留低消耗触发器电路，其包括至少一个触发器（10）和至少一个保持细胞;连接到所述触发器的输出端，并且被配置以便做到（20 200） 触发器电路的正常手术期间，保持小区发送的数据或逻辑状态存在触发器到其自己的输出端（SO）的输出端上，而触发器电路的低消耗手术期间 闩锁电路（22; 220）适合于记忆的数据或逻辑状态对应于本触发器的输出端子上的负载的数据或逻辑状态保持单元的被激活。
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