公开(公告)号：EP2348634B1

公开(公告)日：2014-03-19

申请号：EP10197058.0

申请日：2010-12-27

Applicant: STMicroelectronics Srl ,  STMicroelectronics Pvt. Ltd.

Inventor： Veggetti, Andrea Mario ,  Jain, Abhishek ,  Rohilla, Pankaj

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

公开(公告)号：EP2348634A1

公开(公告)日：2011-07-27

申请号：EP10197058.0

申请日：2010-12-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Pvt. Ltd.

Inventor： Veggetti, Andrea Mario ,  Jain, Abhishek ,  Rohilla, Pankaj

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present invention relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop (10) and at least one retention cell (20; 200) connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal (SO), while during low consumption operation of the flip-flop circuit a latch circuit (22; 220) of the retention cell suitable to memorise data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本发明涉及具有数据保留低消耗触发器电路，其包括至少一个触发器（10）和至少一个保持细胞;连接到所述触发器的输出端，并且被配置以便做到（20 200） 触发器电路的正常手术期间，保持小区发送的数据或逻辑状态存在触发器到其自己的输出端（SO）的输出端上，而触发器电路的低消耗手术期间 闩锁电路（22; 220）适合于记忆的数据或逻辑状态对应于本触发器的输出端子上的负载的数据或逻辑状态保持单元的被激活。