公开(公告)号：EP4235500A1

公开(公告)日：2023-08-30

申请号：EP22158957.5

申请日：2022-02-25

Applicant: STMicroelectronics razvoj polprevodnikov d.o.o.

Inventor： PEVEC, Albin ,  SUHADOLNIK, Nejc ,  KUNC, Vinko ,  STIGLIC, Maksimiljan

IPC: G06K19/07 ,  G05F3/08

Abstract: The present disclosure relates to a linear voltage regulator (2) comprising: a first transistor (41) between a first input terminal (21), adapted to receive a first voltage (VCC), and an output terminal (28) adapted to provide a regulated voltage (VCC_OUT); a second transistor (45) between a second input terminal (26), adapted to receive a second voltage, and said output terminal; an amplifier of the difference between a third voltage proportional to the voltage at said output terminal, and a reference voltage (VREF), an output of said amplifier being selectively coupled to respective control terminals (44, 48) of said first and second transistors, said amplifier being supplied by a fourth voltage corresponding to the highest voltage between said first and second voltages.

公开(公告)号：EP3584948A1

公开(公告)日：2019-12-25

申请号：EP18178584.1

申请日：2018-06-19

Applicant: STMicroelectronics razvoj polprevodnikov d.o.o.

Inventor： STIGLIC, Maksimiljan ,  BRATUZ, Iztok ,  PEVEC, Albin ,  BENKOVIC, Roman

IPC: H04B5/00

Abstract: A method for decoding a data stream carried by a modulated signal (SIG), said signal being modulated according to one protocol belonging to the group including protocols A and B of ISO/IEC14443 standard and protocol F of JIS.X.6319 standard, comprising:
receiving said modulated signal (SIG), detecting said protocol and decoding said data stream in accordance with said protocol using a clock signal (CLK), wherein, whatever the detected protocol, said clock signal (CLK) is a clock signal extracted from said received modulated signal (SIG).

公开(公告)号：EP3584949A1

公开(公告)日：2019-12-25

申请号：EP18178585.8

申请日：2018-06-19

Applicant: STMicroelectronics razvoj polprevodnikov d.o.o.

Inventor： STIGLIC, Maksimiljan ,  BRATUZ, Iztok ,  PEVEC, Albin ,  BENKOVIC, Roman

IPC: H04B5/00

Abstract: 1. An integrated circuit having an input configured to receive an induced signal (SIG), said induced signal (SIG) being modulated according to a protocol belonging to the group including protocols using ASK modulation and protocols using OOK modulation, said integrated circuit comprising:
- detection means (DET) configured to detect said modulation;
- decoding means (DEC) configured to detect said protocol.
- a configurable limiter (LIM) configured to limit the level of the induced signal and having a first configuration (MODE1) adapted to protocols using ASK modulation and a second configuration (MODE2) adapted to protocols using OOK modulation;
- control means (CM) configured to set the limiter in said first configuration (MODE1) until protocol is detected, and configured to switch the limiter from said first configuration (MODE1) to said second configuration (MODE2) if a protocol using OOK modulation is detected.

公开(公告)号：EP3413473A1

公开(公告)日：2018-12-12

申请号：EP18174551.4

申请日：2018-05-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics razvoj polprevodnikov d.o.o.

Inventor： TRAMONI, Alexandre ,  CORDIER, Nicolas ,  STIGLIC, Maksimiljan

IPC: H04B5/00 ,  H04W52/00

CPC classification number: H01Q1/002 ,  G01R21/00 ,  G06K7/10 ,  H04B5/0025 ,  H04W52/00

Abstract: Dispositif de communication sans contact, comprenant une antenne (ANT2), des moyens de pilotage (2, D1, D2) possédant une borne d'alimentation (20) destinée a recevoir une tension d'alimentation (Vext) et configurés pour délivrer un courant a destination de l'antenne, et des moyens (MCTRL) de contrôle de la puissance émise par ladite antenne configurés pour, en présence d'une requête de diminution d'un niveau actuel de puissance émise, diminuer la tension d'alimentation (Vext) des moyens de pilotage jusqu'a une valeur cible correspondant a un nouveau niveau de ladite puissance émise inférieur audit niveau actuel.