公开(公告)号：EP4529382A1

公开(公告)日：2025-03-26

申请号：EP24199611.5

申请日：2024-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Hongjun ,  LEE, Kiseok ,  KIM, Huijung ,  SONG, Younggeun ,  LEE, Yongjin

IPC: H10B12/00 ,  H10D30/67

Abstract: A semiconductor device includes bit lines, channels, a first capping pattern, a gate insulation pattern, a gate electrode and capacitors. The bit lines are on a substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in a second direction. The channels are spaced apart from each other in the first direction. The first capping pattern is on a sidewall of each of the channels. The gate insulation pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulation pattern. The capacitors are electrically connected to respective ones of the channels.

公开(公告)号：EP4422369A1

公开(公告)日：2024-08-28

申请号：EP23194716.9

申请日：2023-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Hongjun ,  KIM, Keunnam ,  LEE, Kiseok

IPC: H10B12/00 ,  H01L21/308

CPC classification number: H10B12/482 ,  H10B12/485 ,  H01L21/3081 ,  H01L21/32139

Abstract: A semiconductor device includes a substrate including an active region, a word line and a bit line that overlap the active region while crossing the active region, a bit line capping layer that is disposed on the bit line, a direct contact that connects the active region and the bit line, and a buried contact that is connected to the active region. Opposite sides of the bit line capping layer have asymmetric shapes.

公开(公告)号：EP4518603A2

公开(公告)日：2025-03-05

申请号：EP24191732.7

申请日：2024-07-30

Applicant: Samsung Electronics Co., Ltd

Inventor： KIM, Seungmuk ,  LEE, Kiseok ,  KIM, Keunnam ,  LEE, Hongjun

IPC: H10B12/00 ,  H01L23/522 ,  H10D1/68

Abstract: A semiconductor device includes a first gate structure in a cell region of a substrate, where the substrate includes a peripheral circuit region, a bit line structure on the cell region of the substrate, a cell capacitor structure on the bit line structure, a decoupling capacitor structure on the peripheral circuit region of the substrate, and a second gate structure on the decoupling capacitor structure.