公开(公告)号：SG10201911466SA

公开(公告)日：2020-01-30

申请号：SG10201911466S

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

Abstract: The present invention relates to a semiconductor memory device. More specifically, the semiconductor memory device comprises: a plurality of memory cell transistors vertically stacked on a substrate; a first conductive line connected to a source of at least one of the memory cell transistors; a second conductive line connected to gates of the memory cell transistors; and a capacitor connected to a drain of at least one of the memory cell transistors. The capacitor includes a first electrode horizontally extended in a first direction parallel to the upper surface of the substrate from the drain. One of the first and second conductive lines horizontally extends in a second direction intersecting the first direction, and the other one of the first and second conductive lines vertically extends in a third direction perpendicular to the upper surface of the substrate.

公开(公告)号：SG10201806114YA

公开(公告)日：2019-04-29

申请号：SG10201806114Y

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors. FIG. 26

公开(公告)号：SG10201803458SA

公开(公告)日：2019-02-27

申请号：SG10201803458S

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： HYUN-JUNG LEE ,  DONGSOO WOO ,  JIN-SEONG LEE ,  NAMHO JEON ,  JAEHO HONG

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element. Fig. 2A

公开(公告)号：US20200219884A1

公开(公告)日：2020-07-09

申请号：US16550192

申请日：2019-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JUNG LEE ,  JOON-SEOK MOON ,  DONGSOO WOO

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US20220367514A1

公开(公告)日：2022-11-17

申请号：US17671533

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  SUNGWON YOO ,  KYUNGHWAN LEE ,  JAEHO HONG

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor memory device may include a stack including word lines and interlayer insulating patterns alternatingly stacked on a substrate, the word lines being extended in a first direction parallel to a top surface of the substrate, semiconductor patterns crossing the word lines and having a long axis extended in a second direction parallel to the top surface of the substrate, data storage patterns respectively interposed between the semiconductor patterns and the word lines, the data storage patterns including a ferroelectric material, bit lines extended in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, each of the bit lines being in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction, and a source line in contact with second side surfaces of the semiconductor patterns.

公开(公告)号：US20220406797A1

公开(公告)日：2022-12-22

申请号：US17679255

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.

公开(公告)号：US20210210494A1

公开(公告)日：2021-07-08

申请号：US17186936

申请日：2021-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JUNG LEE ,  JOON-SEOK MOON ,  DONGSOO WOO

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/06

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US20240243059A1

公开(公告)日：2024-07-18

申请号：US18372881

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  JUNSOO KIM ,  ILGWEON KIM ,  DONGSOO WOO ,  MOONYOUNG JEONG ,  JOON HAN

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including an insulating substrate. A semiconductor layer is on the substrate. An active pattern is on the semiconductor layer. A bit line is disposed in the insulating substrate. The bit line extends along a first direction parallel to a bottom surface of the substrate. A buried node contact penetrates the semiconductor layer in a direction perpendicular to the bottom surface of the substrate. A word line penetrates the active pattern in a second direction that is parallel to the bottom surface of the substrate and crosses the first direction. The active pattern may be connected to the bit line through the buried node contact. A top surface of the buried node contact may be higher than a bottom surface of the active pattern.

公开(公告)号：US20230115434A1

公开(公告)日：2023-04-13

申请号：US17868944

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  JONGMAN PARK ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/11507

Abstract: Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.

公开(公告)号：US20220302124A1

公开(公告)日：2022-09-22

申请号：US17837962

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JUNG LEE ,  JOON-SEOK MOON ,  DONGSOO WOO

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.