公开(公告)号：US11075088B2

公开(公告)日：2021-07-27

申请号：US16812925

申请日：2020-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyong Park ,  Namjun Kang ,  Dougyong Sung ,  Seungbo Shim ,  Junghyun Cho ,  Myungsun Choi

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/67 ,  H01L27/11582 ,  H01L49/02 ,  H01J37/32

Abstract: Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz.

公开(公告)号：US20240162130A1

公开(公告)日：2024-05-16

申请号：US18223757

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Seungmin Baek ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827

Abstract: A semiconductor package includes a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface, a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer, a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires, and a semiconductor substrate disposed on an upper surface of the third redistribution wire layer, the semiconductor substrate including at least one memory semiconductor chip electrically connected to the fourth redistribution wires.

公开(公告)号：US11626362B2

公开(公告)日：2023-04-11

申请号：US17333615

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

公开(公告)号：US20200234964A1

公开(公告)日：2020-07-23

申请号：US16812925

申请日：2020-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyong Park ,  Namjun Kang ,  Dougyong Sung ,  Seungbo Shim ,  Junghyun Cho ,  Myungsun Choi

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/311 ,  H01L21/67

Abstract: Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz.

公开(公告)号：US20170229312A1

公开(公告)日：2017-08-10

申请号：US15423003

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyong PARK ,  Namjun Kang ,  Dougyong Sung ,  Seungbo Shim ,  Junghyun Cho ,  Myungsun Choi

IPC: H01L21/3065 ,  H01L21/311 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/32532 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/67069 ,  H01L27/11582 ,  H01L28/90

Abstract: Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz.

公开(公告)号：US09721762B2

公开(公告)日：2017-08-01

申请号：US14473554

申请日：2014-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounghoon Han ,  Byungbok Kang ,  Namjun Kang ,  Tae-Hwa Kim ,  Junghyun Cho ,  Jae-Hyun Lee

IPC: G06F19/00 ,  H01J37/32 ,  G05B23/02

CPC classification number: H01J37/32394 ,  G05B23/0283 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/18 ,  Y02P90/86

Abstract: Provided are a method and a system for managing semiconductor manufacturing equipment. The method may be performed using an equipment computer and may include ordering to perform a preventive maintenance to a chamber and parts in the chamber, monitoring a result of the preventive maintenance to the chamber and the parts, and performing a manufacturing process using plasma reaction in the chamber, if the result of the preventive maintenance is normal. The monitoring the result of the preventive maintenance may include a pre-screening method monitoring the result of the preventive maintenance using electric reflection coefficients obtained from the chamber and the parts without using the plasma reaction.

公开(公告)号：US11923214B2

公开(公告)日：2024-03-05

申请号：US17337709

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Sang-Geun Park ,  Dongseok Baek ,  Jaehyuk Choi

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/67132 ,  H01L21/67092 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67259 ,  H01L21/67288 ,  H01L21/6835 ,  H01L22/12 ,  H01L23/3121 ,  H01L23/481 ,  H01L21/56 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68395 ,  H01L2224/13023 ,  H01L2224/13025

Abstract: A semiconductor packaging apparatus and methods of manufacturing semiconductor devices using the same. The semiconductor packaging apparatus includes a process unit, and a controller associated with the process unit. The process unit includes a bonding part that bonds a semiconductor substrate and a carrier substrate to each other to form a bonded substrate, a cooling part that cools the bonded substrate, and a detection part in the cooling part and configured to detect a defect of the bonded substrate. The controller is configured to control the process unit using data obtained from the detection part.

公开(公告)号：US11296148B2

公开(公告)日：2022-04-05

申请号：US17027992

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535

Abstract: A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.

公开(公告)号：US11031328B2

公开(公告)日：2021-06-08

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US10971333B2

公开(公告)日：2021-04-06

申请号：US15723837

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hyub Lee ,  Dougyong Sung ,  Je-Hun Woo ,  Bongseong Kim ,  Juho Lee ,  Yun-Kwang Jeon ,  Junghyun Cho

IPC: H01J37/32 ,  H01L21/67

Abstract: Embodiments of the inventive concepts provide antennas, plasma generating circuits, plasma processing apparatus, and methods for manufacturing semiconductor devices using the same. The circuits include radio-frequency power sources generating radio-frequency powers, antennas receiving the radio-frequency powers to generate plasma and having a first mutual inductance, and inductors connecting the antennas to the radio-frequency power sources, respectively. The inductors have a second mutual inductance reducing and/or canceling the first mutual inductance.