公开(公告)号：EP4326028A1

公开(公告)日：2024-02-21

申请号：EP23162740.7

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiheun ,  KIM, Yongseok ,  KIM, Hyuncheol ,  MYEONG, Ilho ,  HA, Daewon

IPC: H10B51/10 ,  H10B51/20 ,  H10B51/30 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes first (CAR1) and second (CAR2) cell arrays. The first cell array includes a first gate electrode (GE1) that extends in a vertical direction (D2), a first channel pattern (CH1) on a side surface (GE1_S) of the first gate electrode, and a first bit line (BL1) electrically connected to the first channel pattern. The second cell array includes a second gate electrode (GE2) that extends in the vertical direction, a second channel pattern (CH2) on a side surface (GE2_S) of the second gate electrode, and a second bit line (BL2) electrically connected to the second channel pattern. A first bit line pad (BLP1) is electrically connected to the first bit line and a second bit line pad (BLP2) is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.