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公开(公告)号:US20220115382A1
公开(公告)日:2022-04-14
申请号:US17555829
申请日:2021-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjun LEE , Sang Chul SHIN , Bong-Soo KIM , Jiyoung KIM
IPC: H01L27/108 , G11C5/06 , H01L21/768 , H01L23/528
Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.
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2.
公开(公告)号:US20190214358A1
公开(公告)日:2019-07-11
申请号:US16038334
申请日:2018-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang Su HA , Gun Rae KIM , Cheol Hyeon PARK , In Hak BAICK , Sang Chul SHIN
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L23/562 , H01L24/08 , H01L24/11 , H01L24/32 , H01L24/81 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079
Abstract: A semiconductor device including a high-reliability bump structure including a pillar structure is provided. The semiconductor device includes a substrate, a connection pad on the substrate, and a bump structure on the connection pad, wherein the bump structure includes a pillar structure having a side wall and an upper surface, a metal protection film including a first portion extending along the side wall of the pillar structure and a second portion extending along the upper surface of the pillar structure, and a solder layer on the second portion of the metal protection film.
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