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公开(公告)号：US11903222B2
公开(公告)日：2024-02-13
申请号：US18185817
申请日：2023-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Seyun Kim , Jinhong Kim , Soichiro Mizusaki , Youngjin Cho
CPC classification number: H10B63/84 , H10B63/34 , H10N70/011 , H10N70/231 , H10N70/841 , H10N70/8828 , H10N70/8833
Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.
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公开(公告)号：US11856873B2
公开(公告)日：2023-12-26
申请号：US17395040
申请日：2021-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Soichiro Mizusaki , Doyoon Kim , Seyun Kim , Yumin Kim , Jinhong Kim , Youngjin Cho
CPC classification number: H10N70/24 , H10B63/34 , H10B63/845 , H10N70/8833
Abstract: A variable resistance memory may include first and second conductive elements spaced apart from each other on a variable resistance layer. The variable resistance layer may include first to third oxide layers sequentially arranged in a direction perpendicular to a direction in which the first and second conductive elements are arranged. A dielectric constant of the second oxide layer may be greater than dielectric constants of the first and third oxide layers.
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公开(公告)号：US11672131B2
公开(公告)日：2023-06-06
申请号：US17317154
申请日：2021-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Seyun Kim , Jinhong Kim , Soichiro Mizusaki , Youngjin Cho
CPC classification number: H01L27/2481 , H01L27/2454 , H01L45/06 , H01L45/1253 , H01L45/144 , H01L45/146 , H01L45/16
Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.
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公开(公告)号：US12063876B2
公开(公告)日：2024-08-13
申请号：US17399194
申请日：2021-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seyun Kim , Doyoon Kim , Yumin Kim , Jinhong Kim , Soichiro Mizusaki , Youngjin Cho
CPC classification number: H10N70/8836 , H10B63/34 , H10N70/253 , H10N70/826 , H10N70/8833 , H10B63/84
Abstract: A variable resistance memory device includes a variable resistance layer and a first conductive element and a second conductive element which are spaced apart from each other on the variable resistance layer. The variable resistance layer may include a first layer and a second layer on the first layer. The first layer includes a ternary or more metal oxide containing two or more metal materials having different valences. The second layer may include silicon oxide. The variable resistance memory device may have a wide range of resistance variation due to the metal oxide in which oxygen vacancies are easily formed. The first conductive element and the second conductive element, in response to an applied voltage, may be configured to form a current path in a direction perpendicular to a direction in which the first layer and the second direction are stacked.
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公开(公告)号：US12027215B2
公开(公告)日：2024-07-02
申请号：US18058555
申请日：2022-11-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Seyun Kim , Jinhong Kim , Soichiro Mizusaki , Youngjin Cho
Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.
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Patent Agency Ranking
公开(公告)号：US20240215250A1
公开(公告)日：2024-06-27
申请号：US18340419
申请日：2023-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seyun KIM , Jooheon Kang , Yumin Kim , Garam Park , Hyunjae Song , Dongho Ahn , Seungyeul Yang , Myunghun Woo , Jinwoo Lee , Seungdam Hyun
CPC classification number: H10B43/35 , G11C16/0483 , H10B43/10 , H10B43/27
Abstract: A memory device including the vertical stack structure includes a gate electrode, a resistance change layer, a channel between the gate electrode and the resistance change layer, and an island structure between the resistance change layer and the channel and in contact with the resistance change layer and the channel, and a gate insulating layer between the gate electrode and the channel.
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公开(公告)号：US20240065000A1
公开(公告)日：2024-02-22
申请号：US18169436
申请日：2023-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Jooheon Kang , Sunho Kim , Seyun Kim , Garam Park , Hyunjae Song , Dongho Ahn , Seungyeul Yang , Myunghun Woo , Jinwoo Lee
CPC classification number: H10B63/34 , G11C13/0007 , G11C13/003 , H10B63/845 , G06N3/063 , G11C2213/71 , G11C2213/75 , G11C2213/79
Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.
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公开(公告)号：US12268009B2
公开(公告)日：2025-04-01
申请号：US17685942
申请日：2022-03-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Doyoon Kim , Seyun Kim , Hyunjae Song , Seungyeul Yang
Abstract: Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.
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公开(公告)号：US20240242743A1
公开(公告)日：2024-07-18
申请号：US18368907
申请日：2023-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jihyun Park , Jungyu Lee , Yumin Kim , Chiweon Yoon , Eunchan Lee
CPC classification number: G11C7/04 , G11C7/08 , G11C7/1063 , G11C7/14
Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a voltage generator configured to output a first voltage that varies according to temperature of the memory device, a second voltage that is constant regardless of the temperature, and a first reference voltage applied to at least one line among the plurality of word lines and the plurality of bit lines, and a temperature compensation circuit configured to generate a compensation offset voltage based on the first voltage and the second voltage, and output a second reference voltage based on the first reference voltage and the compensation offset voltage.
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公开(公告)号：US20240233844A1
公开(公告)日：2024-07-11
申请号：US18471430
申请日：2023-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eunchan Lee , Jungyu Lee , Yumin Kim , Jihyun Park , Jayang Yoon
CPC classification number: G11C16/3495 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/3459
Abstract: A device includes a first current mirror circuit including a plurality of first transistors, the plurality of first transistors including a common gate configured to receive a decoding signal according to a number of fail bits that are program-failed, a second current mirror circuit including a plurality of second transistors including a common gate configured to receive a reference current signal and a plurality of resistors respectively electrically connected to respective first terminals of the second transistors, and a comparison circuit configured to determine a compared result by comparing a first voltage corresponding to the decoding signal with respective ones of a plurality of second voltages output from the second current mirror circuit and configured to output a count signal corresponding to the compared result.
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