公开(公告)号：US20030141605A1

公开(公告)日：2003-07-31

申请号：US10191157

申请日：2002-07-09

Applicant: Silicon Integrated Systems Corp.

Inventor： Shyh-Dar Lee ,  Chen-Chiu Hsue

IPC: H01L023/544

CPC classification number: H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an identifying mark on a semiconductor wafer. The identifying mark, for example a bar code or a character of patterns or words, is formed on the side wall of the semiconductor wafer to avoid contamination and the creation of failure dies during the formation of the identifying mark.

Abstract translation: 一种在半导体晶片上形成识别标记的方法。 在半导体晶片的侧壁上形成识别标记，例如条形码或图案或字的字符，以避免在形成识别标记期间的污染和产生故障模具。

公开(公告)号：US20020167090A1

公开(公告)日：2002-11-14

申请号：US10108611

申请日：2002-03-27

Applicant: Silicon Integrated Systems Corp.

Inventor： Chen-Chiu Hsue ,  Shyh-Dar Lee

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract translation: 本发明提供一种具有电容器的双镶嵌结构。 在形成薄膜电容器之前，通过镶嵌工艺用Cu金属制造底层互连。 电容器通过沉积第一金属层，绝缘体和第二金属层而形成。 然后，对堆叠的层进行两次掩模和蚀刻处理以形成薄膜电容器和金属线。 在形成电容器之后，通过镶嵌工艺用Cu金属制造上互连。

公开(公告)号：US20020155695A1

公开(公告)日：2002-10-24

申请号：US09841568

申请日：2001-04-19

Applicant: Silicon Integrated Systems Corp.

Inventor： Shyh-Dar Lee ,  Chen-Chiu Hsue

IPC: H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/0223 ,  H01L21/0212 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract translation: 双镶嵌工艺应用于具有双镶嵌开口的半导体衬底，其具有暴露金属线并被第一低k电介质层包围的通孔，以及位于通孔上方并被第二个 低k电介质层。 用作介电阻挡层的原位氧化物衬垫形成在第一低k电介质层和第二低k电介质层的侧壁上。 金属阻挡层共形沉积在半导体衬底的暴露表面上以覆盖双镶嵌开口的侧壁和底部。 双镶嵌开口填充有导电层，然后通过CMP工艺抛光沟槽水平面外的剩余导电层。