公开(公告)号：US20040181722A1

公开(公告)日：2004-09-16

申请号：US10401701

申请日：2003-03-31

Applicant: Silicon Integrated Systems Corp.

Inventor： Juinn Lee ,  Chin-Pin Jen ,  Ming-Chang Yang ,  Hung-Chieh Chen

IPC: G01R031/28 ,  H03M013/00

CPC classification number: G01R31/318569 ,  G01R31/318566 ,  G01R31/3191

Abstract: For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.

Abstract translation: 对于多个逻辑集成电路，从每个对应的扫描链集中检索与触发器相关联的初始值向量。 将相同对应的扫描链集合的初始值向量彼此进行比较，以便在初始值向量中识别具有固定值的元素。 当具有固定值的元素的总数达到预定百分比时，具有固定值的元素被选择为相应的扫描链集合的金色图案。 在测试期间，将要测试的逻辑集成电路的扫描链的初始值向量与与扫描链相关联的黄金模式进行比较，以确定在逻辑的扫描链中是否存在故障触发器 集成电路进行测试。