公开(公告)号：EP0822584A3

公开(公告)日：1998-05-13

申请号：EP97305641.9

申请日：1997-07-28

Applicant: Surface Technology Systems Limited

Inventor： Bhardwaj, Jyoti Kiron ,  Ashraf, Huma ,  Khamsehpour, Babak ,  Hopkins, Janet ,  Ryan, Martin Edward ,  Haynes, David Mark ,  Hynes, Alan Michael

IPC: H01L21/312 ,  H01L21/306

CPC classification number: H01L21/30655 ,  H01L21/3086 ,  H01L21/312

Abstract: A method of depositing a side wall passivation layer on an etched feature in a semiconductor substrate, comprising placing the substrate in a vacuum chamber, striking a plasma, and introducing a hydrocarbon deposition gas to deposit a carbon or hydrocarbon layer.

公开(公告)号：EP0822582A3

公开(公告)日：1998-05-13

申请号：EP97305642.7

申请日：1997-07-28

Applicant: Surface Technology Systems Limited

Inventor： Bhardwaj, Jyoti Kiron ,  Ashraf, Huma ,  Khamsehpour, Babak ,  Hopkins, Janet ,  Hynes, Alan Michael ,  Ryan, Martin Edward ,  Haynes, David Mark

IPC: H01L21/306

CPC classification number: H01L21/30655

Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

Abstract translation: 本发明涉及用于处理半导体衬底的方法，特别是一种使用交替的反应离子蚀刻在反应室中蚀刻半导体衬底中的沟槽并通过化学气相沉积沉积钝化层的方法，其中一个或多个以下参数 ：气体流速，腔室压力，等离子体功率，衬底偏压，蚀刻速率，沉积速率在一个周期内变化。

公开(公告)号：EP0822584A2

公开(公告)日：1998-02-04

申请号：EP97305641.9

申请日：1997-07-28

Applicant: Surface Technology Systems Limited

Inventor： Bhardwaj, Jyoti Kiron ,  Ashraf, Huma ,  Khamsehpour, Babak ,  Hopkins, Janet ,  Ryan, Martin Edward ,  Haynes, David Mark ,  Hynes, Alan Michael

IPC: H01L21/312 ,  H01L21/306

CPC classification number: H01L21/30655 ,  H01L21/3086 ,  H01L21/312

Abstract: A method of depositing a side wall passivation layer on an etched feature in a semiconductor substrate, comprising placing the substrate in a vacuum chamber, striking a plasma, and introducing a hydrocarbon deposition gas to deposit a carbon or hydrocarbon layer.

Abstract translation: 一种在半导体衬底中的蚀刻特征上沉积侧壁钝化层的方法，包括将衬底放置在真空室中，撞击等离子体，并且引入烃沉积气体以沉积碳或烃层。

公开(公告)号：EP0822582A2

公开(公告)日：1998-02-04

申请号：EP97305642.7

申请日：1997-07-28

Applicant: Surface Technology Systems Limited

Inventor： Bhardwaj, Jyoti Kiron ,  Ashraf, Huma ,  Khamsehpour, Babak ,  Hopkins, Janet ,  Hynes, Alan Michael ,  Ryan, Martin Edward ,  Haynes, David Mark

IPC: H01L21/306

CPC classification number: H01L21/30655

Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

Abstract translation: 本发明涉及用于处理半导体衬底的方法，具体涉及使用交替反应离子蚀刻和通过化学气相沉积沉积钝化层来蚀刻反应室中的半导体衬底中的沟槽的方法，其中一个或多个以下参数 ：气体流速，室压力，等离子体功率，衬底偏压，蚀刻速率，沉积速率，循环时间和蚀刻/沉积比随时间变化。