公开(公告)号：JPH04273506A

公开(公告)日：1992-09-29

申请号：JP25209991

申请日：1991-09-30

Applicant: TANDEM COMPUTERS INC

Inventor： RENAADO II OOBUAAHAUSU ,  DANIERU II RENOSUKII

IPC: G06F1/06 ,  G06F1/12 ,  G06F13/36 ,  G06F13/42 ,  G06F15/78

Abstract: PURPOSE: To provide a synchronous processor unit which performs the communication between its two divided parts which are clocked at different frequency levels after connecting both parts together via a buffer unit. CONSTITUTION: The synchronous processor 102 is divided into two parts and clocked by the different clock signals. A part 12 including an instruction execution unit 20 and an instruction and data memory 24 is clocked by the frequency of a higher level. On the other hand, the other part 14 of the processor 102 including the processor elements which are not frequently used is clocked by the frequency of a lower level. The elements of both parts 12 and 14 are connected together via the individual data buses and also selectively connected to each other via a buffer unit 62. The signal generated by a clock signal generation unit 70 also monitors the instructions that are carried out by the unit 20. When the communication is performed between the parts 12 and 14, the clocks of high and low speeds are synchronized with each other and the buses of both parts are connected together via the unit 62.

公开(公告)号：JPS63262725A

公开(公告)日：1988-10-31

申请号：JP7169288

申请日：1988-03-25

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU II RENOSUKII

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28

公开(公告)号：JPS6446834A

公开(公告)日：1989-02-21

申请号：JP7169388

申请日：1988-03-25

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU II RENOSUKII

IPC: G06F9/32

Abstract: PURPOSE: To eliminate the necessity of additional hardware and timing delay by using a specified group relative address specification system. CONSTITUTION: A memory 10 has a branch instruction(BR) 12, a literal field(LIT) 14 and an address specification instruction TARG 16. The upper bits of a 1st address are converted into the upper bits of a 2nd address by hardware controlled by a selected numeral within the LIT 14 including numerals supplied from the external. The converted upper bits of the 1st address and a subset of numerals supplied by the LIT 14 are combined to form the 2nd selected address. Consequently, the offset of both of positive and negative values from an optional program counter address(PC) value can be guaranteed without requiring excess hardware and time delay.