IMPROVED VLSI PACKAGE HAVING A PLURALITY OF POWER PLANE

    公开(公告)号:JPS6489349A

    公开(公告)日:1989-04-03

    申请号:JP14669188

    申请日:1988-06-14

    Abstract: PURPOSE: To match two different semiconductor chips by realigning the terminal of a package with the power pad and power plane of the package using vias. CONSTITUTION: A package 10 comprises a package body 12 having a plane provided with pins 16. Pins 16a, 16b project outward from a plane 14 at a position close to a recess 18 where a semiconductor chip is located. A chip 20 is connected through a bonding wire 22 with a pair of power pads 24 for supplying a different voltage to the chip 20. Each pad 24 is connected through an outer via 42 with each pin 16a and each power plane in a group of power planes 34, 36, 38 and 40. Matching is effected by using an inner via in conjunction with a via 42 in the package. One inner via corresponds to one outer via.

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