公开(公告)号：JPH0773059A

公开(公告)日：1995-03-17

申请号：JP5657794

申请日：1994-03-02

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO EI BURUBA ,  JIEIMUZU ESU KURETSUKA ,  KAIRAN TABURIYU FUEI JIYUNIA ,  RARII ERU RAMANO ,  NIKIIRU EI MEETA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16

Abstract: PURPOSE: To sufficiently and effectively utilize the high-speed throughput of a high-speed processor, in a fault-tolerant computer system. CONSTITUTION: Concerning this fault tolerant type computer system, a multiplex CPU is used for executing the same instruction stream at independent clock cycle timing. The CPU internally executes instructions until its input or output operation requires access to a memory or a device asynchronous with a local CPU clock. Concerning such an input/output operation, each CPU is forced to complete the input/output operation by using the equal number of clock cycles. When the input/output operation is completed, the clocks for the internal processing of the instruction stream are put in order inside each CPU but these clocks are continued while being possible disconnected in real time by drift of an oscillator. The accumulated drift is periodically removed by timer interruption for synchronizing the CPU with each other in real time.