公开(公告)号：JPH0887338A

公开(公告)日：1996-04-02

申请号：JP16185895

申请日：1995-06-28

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO ERU OORUDORITSUJI ,  UIRIAMU PII BANTON ,  SUTEIIBUN AARU BIISERU ,  DEIBUITSUDO BURAUN ,  DANIERU DEII GAN ,  KAARU KAAGII ,  DEIBUITSUDO PII SOONIA

IPC: H02J9/00 ,  G01R31/28 ,  G01R31/40 ,  G05F1/00 ,  G06F11/00 ,  G06F11/20 ,  H02J1/00 ,  H02J9/06

Abstract: PURPOSE: To test a potential fault in a power mixing device by providing first and second power rail and the power mixing device in a circuit module. CONSTITUTION: The first power rail 30 of a circuit 10 is connected to the input of a DC controller(DCC) 32 through a first fuse 34, a first power path transistor 36 and a first isolation diode 38 which are mutually serially connected. Similarly a second power rail 40 is connected to the input of DCC 32 through a second fuse 44, a second power path transistor 46 and a second isolation diode 48 which are mutually serially connected. In addition a first test circuit 80 is provided with a first test opto-isolator 82 and its control input is connected to a first test node 84 arranged between the drain of a first power path N-channel MOS transistor 36 and the cathode of the first isolation diode 38. Consequently, a potential fault test is made possible at the power mixing device.

公开(公告)号：JPH0866015A

公开(公告)日：1996-03-08

申请号：JP16185995

申请日：1995-06-28

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO ERU OORUDORITSUJI ,  SUTEIIBUN AARU BIISERU ,  DANIERU DEII GAN

IPC: G06F1/26 ,  G05F1/10 ,  G06F1/18 ,  G06F1/30 ,  G06F11/00 ,  H02H3/05 ,  H02H9/00 ,  H02J1/10 ,  H02M3/00

Abstract: PURPOSE: To protect a logical unit circuit from the transient state of power and power fluctuation by changing over power-supply inputs from alternating power supplies. CONSTITUTION: First and second enable circuits 40, 50 generate signals which select whether or not power is supplied from first and/or second power supplies 20, 30. First and second inrush limiters 60, 70 limit the time change rate of a current flowed through a DC converter 120, in response to the enable signals. First and second open circuits 80, 90 connect the first and second inrush limiters 60, 70 and the DC converter 120 to the first and second enable circuits 40, 50, when the circuits 80, 90 are connected to first and second pair short-circuit pins 73, 83. The first and second pair short-circuit pins 73, 83 are conjoined with the first and second open circuits 80, 90 respectively when a logical unit 10 is inserted completely to a computer housing, but the short-circuit pins 73, 83 are not connected, when the logical unit 10 is not completely inserted into the computer housing.