公开(公告)号：JPH0855076A

公开(公告)日：1996-02-27

申请号：JP15256595

申请日：1995-05-25

Applicant: TANDEM COMPUTERS INC

Inventor： TOOMASU DABURIYU SABEEJI

IPC: G06F13/14 ,  G06F12/06

Abstract: PURPOSE: To comparatively easily establish address sequence required in specified use by continuing a step for generating a bit pattern showing a next address until the last address in sequence is obtained. CONSTITUTION: A plural bits address bus 25 mounting a physical device address is provided for an SCSI bus 10 and the bus 10 is connected to a host device generating plural bit codes called as anchor patterns given to the upper end part 27 of the bus 25. The address bus 25 has plural anchor pattern conversion elements 28 on the intermediate positions of the connection point of the SCSI bus device. The orders of 0-13 are given to fourteen conductors in the address bus 25 and three tap connections extend from the conductor numbers 1, 4 and 10. In the respective conversion elements 28, the conductors of respective fields are connected so that they execute one rank shift of the respective conductors in a designated direction at every field. The last conductor in a shift direction is returned and connected to the first conductor in the field.