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    Diagnostic apparatus for a data processing system
    4.
    发明公开
    Diagnostic apparatus for a data processing system 失效
    诊断数据系统。

    公开(公告)号：EP0289158A2

    公开(公告)日：1988-11-02

    申请号：EP88303221.1

    申请日：1988-04-11

    Applicant: TANDEM COMPUTERS INCORPORATED

    Inventor： Lenoski, Daniel E. ,  Garcia, David J.

    IPC: G06F11/26

    CPC classification number: G01R31/318552

    Abstract: The present invention is directed to a level sensitive diagnostic apparatus for a data processing component. The diagnostic apparatus requires only two free-running, non-overlapping clocks, and it may be controlled by software based enabling signals. In one embodiment of the present invention, each scan unit in a shift register chain comprises a plurality of level sensitive elements, e.g., data latches, which transfer signals from their input terminals to their output terminals in response to a "Phase B" pulse train. A multiplexer is connected to each data latch for commu­nicating run data to the input terminal of each data latch in a normal mode of operation. In test mode, the multiplexer communicates signals from the output terminal of one data latch to the input terminal of an adjacent data latch, so that the data latch signals are serially communicated through the resulting latch chain. The first latch in the series is connected to a test data input, and the last latch in the series is connected to a test data output.
    In order to prevent the test data from propagating uncontrollably through the serially connec­ted latches, each multiplexer includes a test latch disposed between the test data input of the multiplexer and the output terminal of the preceding data latch in the chain. The test latch is controlled by a "Phase A" pulse train signal which is interleaved with but does not overlap the phase B pulse train, and each phase A positive pulse alternates with each phase B pulse. For controlling the multiplexers, a scan enable signal is connected to each multiplexer through a select latch for ensuring that the multiplexers operate synchronously with the test data appearing on the multiplexer inputs. For maintaining the existing values at the output terminals of each data latch when desired, a FREEZE signal is connected to the enable terminal of each run data latch through a freeze latch.

    Abstract translation: 本发明涉及一种用于数据处理部件的电平敏感诊断装置。 诊断装置仅需要两个自由运行的非重叠时钟，并且可以由基于软件的启用信号来控制。 在本发明的一个实施例中，移位寄存器链中的每个扫描单元包括多个电平敏感元件，例如数据锁存器，其响应于“B相”脉冲串将信号从它们的输入端传送到它们的输出端 。 多路复用器连接到每个数据锁存器，用于在正常操作模式下将运行数据传送到每个数据锁存器的输入端。 在测试模式下，多路复用器将来自一个数据锁存器的输出端的信号传送到相邻数据锁存器的输入端，使数据锁存信号通过产生的锁存链进行串行通信。 该系列中的第一个锁存器连接到测试数据输入，该系列中的最后一个锁存器连接到测试数据输出。 为了防止测试数据通过串行连接的锁存器不受控制地传播，每个多路复用器包括设置在多路复用器的测试数据输入和链中先前数据锁存器的输出端之间的测试锁存器。 测试锁存器由与相B脉冲序列交错但不重叠的“A相”脉冲串信号控制，每相A正脉冲与每相B脉冲交替。 为了控制多路复用器，扫描使能信号通过选择锁存器连接到每个多路复用器，以确保复用器与出现在多路复用器输入端上的测试数据同步工作。 为了在需要时保持每个数据锁存器的输出端子上的现有值，通过冻结锁存器将一个FREEZE信号连接到每个运行数据锁存器的使能端。

    Fault-tolerant multiprocessor system
    6.
    发明公开
    Fault-tolerant multiprocessor system 失效
    Fehlertolerantes Multiprozessorsystem

    公开(公告)号：EP0747833A2

    公开(公告)日：1996-12-11

    申请号：EP96304182.7

    申请日：1996-06-06

    Applicant: TANDEM COMPUTERS INCORPORATED

    Inventor： Horst, Robert W. ,  Garcia, David J.

    IPC: G06F15/16 ,  G06F11/00

    CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.
    Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
    CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

    Abstract translation: 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过路由设备互连，该路由设备也互连子处理器系统。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个存储器访问被拒绝。

    Scan test apparatus for digital systems having dynamic random access memory
    9.
    发明公开
    Scan test apparatus for digital systems having dynamic random access memory 失效
    Abfrageprüfgerätfürdigitale Systeme mit dynamischem Direktzugriffspeicher。

    公开(公告)号：EP0287303A2

    公开(公告)日：1988-10-19

    申请号：EP88303223.7

    申请日：1988-04-11

    Applicant: TANDEM COMPUTERS INCORPORATED

    Inventor： Garcia, David J.

    IPC: G11C29/00 ,  G06F11/26

    CPC classification number: G01R31/31919 ,  G01R31/318385 ,  G01R31/31908 ,  G11C29/32 ,  G11C29/48

    Abstract: A scan test apparatus is constructed to scan test a digital system having a memory system containing dynamic random access memory (DRAM). The scan test apparatus is given access to the memory system so that test control signals can preset the refresh counter (for the DRAM) and initialize the memory for later test­ing.

    Abstract translation: 扫描测试装置被构造为扫描测试具有包含动态随机存取存储器（DRAM）的存储器系统的数字系统。 允许扫描测试装置访问存储器系统，使得测试控制信号可以预置刷新计数器（用于DRAM）并初始化存储器供以后测试。

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