公开(公告)号：EP0747820A2

公开(公告)日：1996-12-11

申请号：EP96304176.9

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Jones, Curtis Willard, Jr. ,  Krause, John C. ,  Simpson, Michael P. ,  Watson, William Joel ,  Sonnier, David Paul ,  Baker, William Edward ,  Bunton, William Patterson ,  Fowler, Daniel L.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involves copying the instruction and data content of the memory of the operating processor to the memory of the waiting processor in a manner that stores the transferred instructions and data in the memory of the waiting processor at locations that correspond to where the instructions and data are located in the memory of the operating processor. Thereafter, the operating processor will periodically send selected ones of the instructions and data to the waiting processor.

Abstract translation: 公开了一种同步一对基本上相同的处理器以进行实质的锁步操作的方法。 其中一个处理器是可操作的，从独占于该处理器的存储器元件执行指令流; 另一个处理器处于等待状态。 该方法涉及将操作处理器的存储器的指令和数据内容以等待处理器的存储器的方式将所传送的指令和数据存储在等待处理器的存储器中的位置处，该位置对应于指令和数据的位置 位于操作处理器的存储器中。 此后，操作处理器将周期性地将选择的指令和数据发送到等待处理器。

公开(公告)号：EP0757315A2

公开(公告)日：1997-02-05

申请号：EP96304175.1

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W. ,  Garcia, David J. ,  Bunton, William Patterson ,  Bruckert, William F. ,  Fowler, Daniel L. ,  Jones, Curtis Willard, Jr. ,  Sonnier, David Paul ,  Watson, William Joel ,  Williams, Frank A.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.
Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract translation: 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过路由设备互连，该路由设备也互连子处理器系统。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个存储器访问被拒绝。

公开(公告)号：EP0747820A3

公开(公告)日：1999-08-18

申请号：EP96304176.9

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Jones, Curtis Willard, Jr. ,  Krause, John C. ,  Simpson, Michael P. ,  Watson, William Joel ,  Sonnier, David Paul ,  Baker, William Edward ,  Bunton, William Patterson ,  Fowler, Daniel L.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involves copying the instruction and data content of the memory of the operating processor to the memory of the waiting processor in a manner that stores the transferred instructions and data in the memory of the waiting processor at locations that correspond to where the instructions and data are located in the memory of the operating processor. Thereafter, the operating processor will periodically send selected ones of the instructions and data to the waiting processor.

公开(公告)号：EP0757315A3

公开(公告)日：1999-08-11

申请号：EP96304175.1

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W. ,  Garcia, David J. ,  Bunton, William Patterson ,  Bruckert, William F. ,  Fowler, Daniel L. ,  Jones, Curtis Willard, Jr. ,  Sonnier, David Paul ,  Watson, William Joel ,  Williams, Frank A.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.