公开(公告)号：EP0747820A2

公开(公告)日：1996-12-11

申请号：EP96304176.9

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Jones, Curtis Willard, Jr. ,  Krause, John C. ,  Simpson, Michael P. ,  Watson, William Joel ,  Sonnier, David Paul ,  Baker, William Edward ,  Bunton, William Patterson ,  Fowler, Daniel L.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involves copying the instruction and data content of the memory of the operating processor to the memory of the waiting processor in a manner that stores the transferred instructions and data in the memory of the waiting processor at locations that correspond to where the instructions and data are located in the memory of the operating processor. Thereafter, the operating processor will periodically send selected ones of the instructions and data to the waiting processor.

Abstract translation: 公开了一种同步一对基本上相同的处理器以进行实质的锁步操作的方法。 其中一个处理器是可操作的，从独占于该处理器的存储器元件执行指令流; 另一个处理器处于等待状态。 该方法涉及将操作处理器的存储器的指令和数据内容以等待处理器的存储器的方式将所传送的指令和数据存储在等待处理器的存储器中的位置处，该位置对应于指令和数据的位置 位于操作处理器的存储器中。 此后，操作处理器将周期性地将选择的指令和数据发送到等待处理器。

公开(公告)号：EP0747820A3

公开(公告)日：1999-08-18

申请号：EP96304176.9

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Jones, Curtis Willard, Jr. ,  Krause, John C. ,  Simpson, Michael P. ,  Watson, William Joel ,  Sonnier, David Paul ,  Baker, William Edward ,  Bunton, William Patterson ,  Fowler, Daniel L.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involves copying the instruction and data content of the memory of the operating processor to the memory of the waiting processor in a manner that stores the transferred instructions and data in the memory of the waiting processor at locations that correspond to where the instructions and data are located in the memory of the operating processor. Thereafter, the operating processor will periodically send selected ones of the instructions and data to the waiting processor.