公开(公告)号：US10892742B2

公开(公告)日：2021-01-12

申请号：US16723508

申请日：2019-12-20

Applicant: Texas Instruments Incorporated

Inventor： Yongseon Koh ,  Roland Ribeiro ,  Horia Giuroiu

IPC: H03K3/017 ,  G06F1/04 ,  H03K5/156

Abstract: A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.

公开(公告)号：US10038577B2

公开(公告)日：2018-07-31

申请号：US15394292

申请日：2016-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Rane ,  Roland Ribeiro ,  Leung Kin Chiu

IPC: H03H7/40 ,  H04L25/03

CPC classification number: H04L25/03949 ,  H04L25/03038 ,  H04L2025/03745

Abstract: One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.

公开(公告)号：US11121851B2

公开(公告)日：2021-09-14

申请号：US16743706

申请日：2020-01-15

Applicant: Texas Instruments Incorporated

Inventor： Manu Basil ,  Mohan Yang ,  Yongseon Koh ,  Roland Ribeiro

IPC: H04L7/04 ,  H03K19/20 ,  H03K5/01 ,  H03L7/08 ,  H03K5/24

Abstract: A system includes a differential clock source configured to provide a reference clock signal and an inverted version of the reference clock signal. The system also includes a quadrature clock source configured to provide a quadrature clock signal that is phase-shifted relative to the reference clock signal. The system also includes a differential sensing circuit coupled to the differential clock source and the quadrature clock source. The differential sensing circuit is configured to determine skew of the quadrature clock signal based on the reference clock signal, the inverted version of the reference clock signal, and the quadrature clock signal.

公开(公告)号：US20180191534A1

公开(公告)日：2018-07-05

申请号：US15394292

申请日：2016-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： AMIT RANE ,  Roland Ribeiro ,  Leung Kin Chiu

IPC: H04L25/03

CPC classification number: H04L25/03949

Abstract: One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.