公开(公告)号：EP0687005B1

公开(公告)日：2004-08-18

申请号：EP95304002.9

申请日：1995-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H. ,  Stoltz, Richard A.

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L21/76837

公开(公告)号：EP0685885B1

公开(公告)日：1999-11-17

申请号：EP95303615.9

申请日：1995-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H. ,  Jeng, Shin-Puu

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0738002A3

公开(公告)日：1998-04-15

申请号：EP96104337.9

申请日：1996-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong, Qi-Zhong ,  Havemann, Robert H.

IPC: H01L21/283

CPC classification number: H01L21/76856 ,  H01L21/76843

Abstract: A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a semiconductor. A metallic diffusion barrier layer, preferably one of TiN, TiW or TiWN and preferably having a thickness of from about 10 nanometers to about 100 nanometers, is deposited on the substrate, preferably by one of sputtering, electron beam evaporation or chemical vapor deposition. The exposed surface of the metallic diffusion barrier layer is treated with a plasma, preferably an oxygen plasma, a nitrous oxide plasma or a plasma of an oxygen-containing species. An electrical conductor, preferably one of aluminum, aluminum-metal alloys, copper or copper-metal alloys and preferably having a thickness of from about 100 nanometers to about 1200 nanometers, is then deposited on the plasma-treated surface of the metallic diffusion barrier layer. The layers can be formed as one of a blanket or continuous films over the substrate. The conductor can then be patterned.

公开(公告)号：EP0809285A1

公开(公告)日：1997-11-26

申请号：EP97106274.0

申请日：1997-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H. ,  Dixit, Girish A. ,  Stoltz, Richard A.

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/0272 ,  H01L21/0331 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/7688 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This is a method of forming a via 39 and a conductor 52 on dielectric layer 40 (which dielectric layer 40 is on an electronic microcircuit substrate 10 which via 39 is electrically connected to a conductive area on the surface of the substrate 10) and a structure formed thereby. The method generally comprises: forming the dielectric layer 30 over the substrate 10; forming a via opening through the insulating layer to expose at least a portion of the conductive area; selectively depositing via metal 39 in the via opening to partially fill the via opening; depositing conductor metal 52 over the dielectric 30 and the selectively deposited via metal 39; and patterning the conductor metal. Generally the via metal and the conductor metal consist essentially of aluminum, copper or combinations thereof. A seed layer 50 (selective deposition initiator) may be used, selected from the group consisting of tungsten, titanium, paladium, platinum, copper, aluminum, and combinations thereof. The conductor metal may be doped with the selectively deposited via metal being doped by dopant diffusion from the conductor metal, thereby avoiding the difficulty of depositing a doped selective metal.

Abstract translation: 这是在电介质层40（电介质层40位于电子微电路基板10上，通孔39电连接到基板10的表面上的导电区域）上形成通孔39和导体52的方法， 由此形成。 该方法通常包括：在衬底10上形成电介质层30; 通过所述绝缘层形成通孔，以暴露所述导电区域的至少一部分; 通过金属39选择性地沉积在通孔开口中以部分地填充通孔开口; 在电介质30和选择性沉积的通孔金属39上沉积导体金属52; 并图案化导体金属。 通常，通孔金属和导体金属基本上由铝，铜或其组合组成。 可以使用种子层50（选择性沉积引发剂），其选自钨，钛，adium，铂，铜，铝及其组合。 导体金属可以掺杂有选择性沉积的通孔金属，其通过掺杂剂从导体金属扩散掺杂，从而避免沉积掺杂的选择性金属的困难。

公开(公告)号：EP0687005A2

公开(公告)日：1995-12-13

申请号：EP95304002.9

申请日：1995-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H. ,  Stoltz, Richard A.

IPC: H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L21/76837

Abstract: A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10 , where the metal layer 14 has a first region 15 and a second region 17 . An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14 . At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14 . A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18 . A structural dielectric layer 26 is deposited between at least the widely-spaced leads. The low-permittivity material 34 is a material with a dielectric constant of less than 3. An advantage of the invention includes improved structural strength by placing structurally weak low-permittivity material only where needed, in areas having closely-spaced leads.

Abstract translation: 一种在紧密间隔的引线之间具有低介电常数材料的半导体器件和方法，以便减少不需要的电容，同时在电容不如关键的宽间距引线之间具有更结构强的电介质。 金属层14沉积在半导体晶片10的基板12上，其中金属层14具有第一区域15和第二区域17.绝缘层39沉积在金属层上，并且绝缘层39被图案化 具有广泛间隔的引线和紧密排列的引线的导体图案。 在金属层14的第一区域15中形成宽间距的引线16.至少相邻的紧密间隔的引线18形成在金属层14的第二区域17中。低介电常数材料34沉积在 紧密间隔的引线18的相邻部分。结构介电层26沉积在至少宽间隔的引线之间。 低介电常数材料34是介电常数小于3的材料。本发明的优点包括通过仅在需要时在具有紧密间隔的引线的区域中放置结构弱的低介电常数材料来提高结构强度。

公开(公告)号：EP0366967A3

公开(公告)日：1991-09-25

申请号：EP89118454.1

申请日：1989-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bell, David A. ,  Havemann, Robert H.

IPC: H01L21/82 ,  H01L21/74

CPC classification number: H01L21/74 ,  H01L21/8249

Abstract: A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer (26) is formed over a portion of a p-type substrate (20) at which an n+ buried doped region (30) is not to be formed, masking the implant for the buried doped region (30). Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide (28) over the surface. The oxide layers (26, 28) are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region (31); the doping concentration of the n+ buried doped region (30) retards diffusion of the boron to the surface thereover. Alternately, a higher, than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer (32) is then grown over the surface, and the n-well (40) is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well (40) by the oxide (42) further planarizes the topography of the device.

公开(公告)号：EP0366967A2

公开(公告)日：1990-05-09

申请号：EP89118454.1

申请日：1989-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bell, David A. ,  Havemann, Robert H.

IPC: H01L21/82 ,  H01L21/74

CPC classification number: H01L21/74 ,  H01L21/8249

Abstract: A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer (26) is formed over a portion of a p-type substrate (20) at which an n+ buried doped region (30) is not to be formed, masking the implant for the buried doped region (30). Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide (28) over the surface. The oxide layers (26, 28) are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region (31); the doping concentration of the n+ buried doped region (30) retards diffusion of the boron to the surface thereover. Alternately, a higher, than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer (32) is then grown over the surface, and the n-well (40) is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well (40) by the oxide (42) further planarizes the topography of the device.

Abstract translation: 一种用于在具有掩埋的掺杂区域的集成电路的制造方法，是游离缺失盘。 热氧化物层（26）形成在以n的哪一个的p型基片（20）的一部分+掩埋的掺杂区域（30）是不形成，掩蔽为掩埋掺杂区（30）的植入物。 植入物的退火，进行在氧化气氛中，生长的表面上进一步氧化（28）。 氧化层（26，28）被去除，并且p型覆盖植入执行用于绝缘目的，并且如果需要清除，以形成p型掩埋掺杂区（31）; 在n +埋掺杂区（30）的掺杂浓度在有延迟了硼对表面的扩散。 可替代地，较高的，比正常掺杂在基底电平可以提供足够的隔离硼。 然后外延层（32）生长在表面上，和n阱（40）是通过注入n型掺杂剂，与由氮化物掩模掩蔽的p阱区形成的; 因此，n阱的退火在氧化环境中进行，所以没有由氧化物（42）一个n阱（40）的一部分的消费进一步平坦化设备的构形。

公开(公告)号：EP0735586B1

公开(公告)日：2002-12-11

申请号：EP96104793.3

申请日：1996-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong, Qi-Zhong ,  Jeng, Shin-Puu ,  Havemann, Robert H.

IPC: H01L23/532

CPC classification number: H01L21/76876 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

公开(公告)号：EP0805491A3

公开(公告)日：1997-11-12

申请号：EP97107086.7

申请日：1997-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H. ,  Jain, Manoj K.

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred embodiments include HSQ (140) as the gap filling low dielectric constant insulator and fluorinated silicon oxide (150) as the between metal level low dielectric constant insulator.

Abstract translation: 具有两种不同低介电常数绝缘体的金属间电介质：一种用于在金属层面内填充空隙（140），另一层（150）在金属层面之间填充。 优选实施例包括作为间隙填充低介电常数绝缘体的HSQ（140）和作为金属级低介电常数绝缘体之间的氟化氧化硅（150）。

公开(公告)号：EP0700080A3

公开(公告)日：1997-06-04

申请号：EP95113239.8

申请日：1995-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Havemann, Robert H.

IPC: H01L21/60

CPC classification number: H01L21/76897

Abstract: A semiconductor device and process for making the same are disclosed which incorporate organic dielectric materials to form self-aligned contacts (SACTs) reliably, even in deep, narrow gaps. In one embodiment, conductors 26 with insulating conductor caps 28 are formed over a silicon substrate 20 with a thin gate oxide 22. A conformal dielectric layer 30, preferably of thermally-grown oxide, is deposited over this structure, which is then covered with an organic-containing layer 32 and an inorganic cap layer 34 (e.g., CVD TEOS). An etch window 38 is patterned in photoresist layer 36 and used as a mask to etch cap window 39 through layer 34, using layer 32 as an etch stop. A second etch removes organic-containing layer 32 in contact widow 41 (and preferably strips photoresist), using conformal layer 30 as an etch stop. A short anisotropic etch may be used to clear conformal layer 30 from gap bottom 43, after which conducting material 40 may be used to make electrical contact to the substrate.