公开(公告)号：US20240259011A1

公开(公告)日：2024-08-01

申请号：US18630020

申请日：2024-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Robert Kenneth OPPEN

IPC: H03K17/0812 ,  G01K7/00 ,  G01R19/10 ,  H03K17/08

CPC classification number: H03K17/0812 ,  G01K7/00 ,  G01R19/10 ,  H03K2017/0806

Abstract: In at least one example, an apparatus includes a logic circuit having a switch control output and first and second logic circuit inputs. A pulse generator has a generator output coupled to the first logic circuit input. An elevated temperature detector has a detector output and a temperature sensor. The detector output is coupled between the second logic circuit input and the temperature sensor.

公开(公告)号：US20230353137A1

公开(公告)日：2023-11-02

申请号：US17732986

申请日：2022-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Robert Kenneth OPPEN

IPC: H03K17/0812 ,  G01K7/00 ,  G01R19/10

CPC classification number: H03K17/0812 ,  G01K7/00 ,  G01R19/10 ,  H03K2017/0806

Abstract: In at least one example, an apparatus includes a logic circuit having a switch control output and first and second logic circuit inputs. A pulse generator has a generator output coupled to the first logic circuit input. An elevated temperature detector has a detector output and a temperature sensor. The detector output is coupled between the second logic circuit input and the temperature sensor.

公开(公告)号：US20220209667A1

公开(公告)日：2022-06-30

申请号：US17135532

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Robert Kenneth OPPEN

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/08

Abstract: In at least some examples, an apparatus includes a logic circuit, first transistor, and second transistor. The logic circuit has a first logic circuit output, and a second logic circuit output. The first transistor has a first transistor gate, a first transistor source, and a first transistor drain, the first transistor gate coupled to the first logic circuit output, the first transistor drain adapted to couple to a voltage source, and the first transistor source coupled to a switching terminal. The second transistor has a second transistor gate, a second transistor source, and a second transistor drain, the second transistor gate coupled to the second logic circuit output, the second transistor drain adapted to couple to the voltage source, and the second transistor source coupled to the switching terminal, wherein a transistor width of the second transistor is larger than a transistor width of the first transistor.