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    DETERMINATION OF POWER MOSFET LEAKAGE CURRENTS
    1.
    发明申请
    DETERMINATION OF POWER MOSFET LEAKAGE CURRENTS 有权

    公开(公告)号：US20210325443A1

    公开(公告)日：2021-10-21

    申请号：US17362706

    申请日：2021-06-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF ,  Henry Litzmann EDWARDS

    IPC: G01R31/26 ,  G01R31/30 ,  G01R19/00 ,  G01R19/165 ,  G01R31/50

    Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

    LOAD RELEASE DETECTION CIRCUIT
    3.
    发明申请
    LOAD RELEASE DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20200169159A1

    公开(公告)日：2020-05-28

    申请号：US16670768

    申请日：2019-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Saurav BANDYOPADHYAY ,  Thomas Matthew LaBELLA ,  Robert Allan NEIDORFF

    IPC: H02M1/08 ,  H03K5/24

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.

    DIGITAL BIT GENERATORS FOR TRIM CIRCUITS
    4.
    发明申请
    DIGITAL BIT GENERATORS FOR TRIM CIRCUITS 有权

    公开(公告)号：US20220399067A1

    公开(公告)日：2022-12-15

    申请号：US17347236

    申请日：2021-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF

    IPC: G11C29/02 ,  G11C5/14

    Abstract: In some examples, a circuit comprises a first polyfuse and a first diode having a first diode anode and a first diode cathode, where the first diode anode is coupled to the first polyfuse. The circuit comprises a second polyfuse coupled to the first polyfuse and a second diode having a second diode anode and a second diode cathode, where the second diode cathode is coupled to the second polyfuse. The circuit comprises a probe pad coupled to the first diode cathode and the second diode anode.

    INTEGRATED CIRCUIT PACKAGE WITH CURRENT SENSE ELEMENT
    5.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH CURRENT SENSE ELEMENT 有权

    公开(公告)号：US20220187337A1

    公开(公告)日：2022-06-16

    申请号：US17364477

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Allan NEIDORFF ,  Sreenivasan K KODURI

    IPC: G01R1/067 ,  H01L23/495 ,  G01R31/28

    Abstract: A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

    SEMICONDUCTOR PROCESS VARIATION DETECTOR
    6.
    发明申请
    SEMICONDUCTOR PROCESS VARIATION DETECTOR 有权

    公开(公告)号：US20210013805A1

    公开(公告)日：2021-01-14

    申请号：US16927558

    申请日：2020-07-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF ,  Saurav BANDYOPADHYAY ,  Ramanathan RAMANI

    IPC: H02M3/158 ,  H02M3/157 ,  H02M1/08

    Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.

    SWITCH CONTROLLER HAVING A DYNAMIC SCALING CIRCUIT
    7.
    发明公开
    SWITCH CONTROLLER HAVING A DYNAMIC SCALING CIRCUIT 审中-公开

    公开(公告)号：US20240291469A1

    公开(公告)日：2024-08-29

    申请号：US18174645

    申请日：2023-02-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF

    IPC: H03K3/012 ,  H02M1/08

    CPC classification number: H03K3/012 ,  H02M1/08

    Abstract: A dynamic scaling circuit includes: a damping control circuit; a sampling circuit; and a controller. The damping control circuit has a first input, a second input, a third input, an output, and a ground terminal. The sampling circuit has a first input, a second input, an output, and a ground terminal. The first input of the sampling circuit is coupled to the output of the damping control circuit. The controller has an input, a first output, a second output, and a third output. The first output of the controller is coupled to the second input of the damping control circuit. The second output of the controller is coupled to the third input of the damping control circuit. The third output of the controller is coupled to the second input of the sampling circuit.

    PROGRESSIVE POWER CONVERTER DRIVE
    10.
    发明申请
    PROGRESSIVE POWER CONVERTER DRIVE 有权

    公开(公告)号：US20220209667A1

    公开(公告)日：2022-06-30

    申请号：US17135532

    申请日：2020-12-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF ,  Robert Kenneth OPPEN

    IPC: H02M3/157 ,  H02M3/158 ,  H02M1/08

    Abstract: In at least some examples, an apparatus includes a logic circuit, first transistor, and second transistor. The logic circuit has a first logic circuit output, and a second logic circuit output. The first transistor has a first transistor gate, a first transistor source, and a first transistor drain, the first transistor gate coupled to the first logic circuit output, the first transistor drain adapted to couple to a voltage source, and the first transistor source coupled to a switching terminal. The second transistor has a second transistor gate, a second transistor source, and a second transistor drain, the second transistor gate coupled to the second logic circuit output, the second transistor drain adapted to couple to the voltage source, and the second transistor source coupled to the switching terminal, wherein a transistor width of the second transistor is larger than a transistor width of the first transistor.

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