公开(公告)号：JPS5721838A

公开(公告)日：1982-02-04

申请号：JP9675280

申请日：1980-07-15

Applicant: Toshiba Corp

Inventor： EGAWA HIDEHARU ,  NISHI YOSHIO ,  MAEGUCHI KENJI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L27/12 ,  H01L21/88

CPC classification number: H01L27/12 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE:To increase the degree of freedom of a multilayer wire by alternately disposing P type and N type epitaxial layers and so disposing P type and N type polysilicon wiring layers to cross with the epitaxial layers. CONSTITUTION:P type and N type epitaxial layers 42, 43 are alternately disposed on a sapphire substrate 41, and N type and P type polysilicon wiring layers 44 and 45 are so disposed as to cross with the layers 42, 43. When this is operated in reverse P-N bias state or in the voltage applied state within P-N contacting potential range in this manner, the crossing between the different conductive semiconductor layers does not make a problem in the circuit operation, an electric contact is formed at the crossing portions 451-454, an electric isolation is performed between the semiconductor layers at the crossing portions 461-464, and since the semiconductor layers can be crossed in the contacted state, the degree of freedom of the wiring can be increased.

Abstract translation: 目的：通过交替设置P型和N型外延层来增加多层线的自由度，从而使P型和N型多晶硅布线层与外延层交叉。 构成：P型和N型外延层42,43交替地设置在蓝宝石衬底41上，并且N型和P型多晶硅布线层44和45被布置成与层42,43交叉。当这被操作时 在反向PN偏置状态或PN接触电位范围内的电压施加状态下，不同的导电半导体层之间的交叉不会在电路操作中产生问题，在交叉部分451-454处形成电接触 在交叉部分461-464处在半导体层之间进行电隔离，并且由于半导体层可以在接触状态下交叉，所以可以提高布线的自由度。

公开(公告)号：JPH05315557A

公开(公告)日：1993-11-26

申请号：JP25988992

申请日：1992-09-29

Applicant: TOSHIBA CORP

Inventor： EGAWA HIDEHARU ,  SUZUKI YASOJI ,  MATSUKI KOJI

IPC: H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To provide a method of manufacturing a semiconductor integrated circuit, where an N-channel and a P-channel transistor can be easily controlled to be nearly equal to each other and adequate in threshold voltage, and both a junction capacitance between the source and the drain region of the N-channel transistor and a substrate bias effect can be made very small. CONSTITUTION:A P-type semiconductor layer 35 higher in impurity concentration than a low-concentration N-type silicon substrate 30 is formed on the N- type silicon substrate 30 through an ion implantation method, and an N-type semiconductor layer 33 of nearly the same impurity concentration with the P-type semiconductor layer 35 is formed on the substrate 30 separate from the P-type semiconductor layer 35 by ion implantation, and thereafter impurity ions of either P-type or N-type are implanted into the surfaces of the P-type semiconductor layer 35 and the N-type silicon substrate 30 at the same time to enable an N-channel transistor and a P-channel transistor to change almost equally in threshold voltage.

公开(公告)号：JPS5721858A

公开(公告)日：1982-02-04

申请号：JP9675180

申请日：1980-07-15

Applicant: Toshiba Corp

Inventor： EGAWA HIDEHARU ,  NISHI YOSHIO ,  MAEGUCHI KENJI

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/12 ,  H01L29/43

CPC classification number: H01L23/53271 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE:To enable forming an ohmic connection between different conductive type layers by interposing high melting point metal or metallic silicide film between different conductive type layers connected to one another in the electrode pickup part of a semiconductor device. CONSTITUTION:N type and P type layers 29, 25 are ohmically contacted by an N type polysilicon layer 271 via high melting point metal or metallic silicide, e.g., the film 26 of Ti, TiSi2, Ta, TaSi2, W, WSi2, M, etc. formed on the layer 25.

Abstract translation: 目的：为了通过在半导体器件的电极拾取部分中彼此连接的不同导电类型层之间插入高熔点金属或金属硅化物膜来实现在不同导电类型层之间形成欧姆连接。 构成：N型和P型层29,25通过高熔点金属或金属硅化物例如Ti，TiSi 2，Ta，TaSi 2，W，WSi 2，M的膜26与N型多晶硅层271欧姆接触， 等形成在层25上。