公开(公告)号：JPH05315557A

公开(公告)日：1993-11-26

申请号：JP25988992

申请日：1992-09-29

Applicant: TOSHIBA CORP

Inventor： EGAWA HIDEHARU ,  SUZUKI YASOJI ,  MATSUKI KOJI

IPC: H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To provide a method of manufacturing a semiconductor integrated circuit, where an N-channel and a P-channel transistor can be easily controlled to be nearly equal to each other and adequate in threshold voltage, and both a junction capacitance between the source and the drain region of the N-channel transistor and a substrate bias effect can be made very small. CONSTITUTION:A P-type semiconductor layer 35 higher in impurity concentration than a low-concentration N-type silicon substrate 30 is formed on the N- type silicon substrate 30 through an ion implantation method, and an N-type semiconductor layer 33 of nearly the same impurity concentration with the P-type semiconductor layer 35 is formed on the substrate 30 separate from the P-type semiconductor layer 35 by ion implantation, and thereafter impurity ions of either P-type or N-type are implanted into the surfaces of the P-type semiconductor layer 35 and the N-type silicon substrate 30 at the same time to enable an N-channel transistor and a P-channel transistor to change almost equally in threshold voltage.

公开(公告)号：JPS63245131A

公开(公告)日：1988-10-12

申请号：JP7857587

申请日：1987-03-31

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: H03M7/00

Abstract: PURPOSE:To surely flow a desired current to a load transistor (TR) by connecting a gate of each load TR of plural logic gate circuits in common to gates of TRs connected with a power supply potential supply terminal of a bias circuit. CONSTITUTION:A bias circuit is provided with a decoder circuit and the bias circuit 11 limits a current flowing to a load P-channel MOS TR. Each gate of load P-channel MOS TRs Tp1-Tp4 is connected in common with each gate of a P-channel MOS Tp11 of the bias circuit 11. Since the P-channel MOS TRs Tp1-Tp4 constitute a current mirror circuit with the P-channel MOS TR Tp11 respectively, output currents flowing through the P-channel MOS TRs Tp1-Tp4 are respectively equal to the current flowing between the power supply terminal Vdd and ground terminal Vss of the bias circuit 11.

公开(公告)号：JPS62286266A

公开(公告)日：1987-12-12

申请号：JP13066786

申请日：1986-06-05

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: H02H7/20 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H03F1/00

Abstract: PURPOSE:To improve surge breakdown withstanding voltage, by connecting a drain and a gate to an output terminal, and setting the threshold voltage of a surge absorbing MOS transistor, whose source is connected to one power source, larger than the range of an open drain output voltage. CONSTITUTION:The drain and the gate of a surge absorbing MOS transistor 28 are connected to the drain of an MOS transistor 15. The source of the MOS transistor 28 is connected to a Vss power source terminal 14. A threshold voltage Vth of the surge absorbing MOS transistor 28 is set at a value higher than the voltage range of an open drain output at the time of operation. Since the threshold voltage of the surge absorbing MOS transistor 28 is higher than the range of the open drain output voltage, the transistor 28 is not operated at the time of normal operation. The protecting operation is performed only when surge is inputted.

公开(公告)号：JPH06132797A

公开(公告)日：1994-05-13

申请号：JP28188592

申请日：1992-10-20

Applicant: TOSHIBA CORP ,  TOSHIBA MICRO ELECTRONICS

Inventor： EBATO KOJI ,  MATSUKI KOJI

IPC: H03K5/135

Abstract: PURPOSE:To reduce a power source noise at the time of switching and to prevent a through current at the time of switching by causing an inverter of a preceding stage which drives the inside of the buffer of a last stage, to execute constant current operation. CONSTITUTION:The inverter 21-1 of the preceding stage, which controls the gate of PMOSFET 19 of the last stage is composed of PMOSFET 31 and NMOSFET 32 which are provided with an input signal IN and NMOSFET 33 between whose drain/source a drain with a source are connected. The gate of NMOSFET 33 is connected to that of NMOSFET 16 in order to mirror a constant current from a constant current generation circuit 10. PMOSFET 31 is provided with large driving capability and in comparison with it, MOSFET 32 is provided with small driving capability. The inverter 21-2 of the preceding stage of NMOSFET 20 is also composed of PMOSFET 41, NMOSFET 42 and PMOSFET 43 and the gate of MOSFET 43 is connected to the output terminal of an operational ampifier 12 in order to execute constant current mirror. Besides, NMOSFET 42 is provided with large driving capability and in comparison with it, P-channel MOSFET 41 is provided with smaller driving capability.

公开(公告)号：JPH02271717A

公开(公告)日：1990-11-06

申请号：JP9261989

申请日：1989-04-12

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI ,  MARUYAMA RYOJI

IPC: H03K23/00 ,  H03K23/64

Abstract: PURPOSE:To form a non-integer frequency division ratio with combination of M and N by constitution comprising a device of a basic frequency divider circuit which is operated at a frequency division ratio of 2M-1 or 2M (M>=2) and an N-notation counter (N is an odd number >=3). CONSTITUTION:A D FFs Q9-Q12, a NAND gate 3 and an OR gate 4 constitute a frequency divider circuit. An outputs of a FF Q11 of the 3rd bit and a FF Q12 of the 4th bit are connected to gates 4, 3. The operation of 1/8 frequency division is attained when a control signal applied to other input C of the gate 4 in the circuit above goes to H and the operation of 1/7 frequency division is attained when the control signal goes to L. A 11-adic counter B connects to a frequency divider circuit A. The operation of the 11-adic counter is circulated while being started from 1/7 frequency division and finished to 1/7 frequency division during 82 sets of input clock periods and the 1/8 frequency division is repeated to an input clock signal IN, a clear signal CLB, node waveforms A-G shown in figure and an output OUT. Thus, a prescribed frequency division ratio, that is, a non-integer frequency division ratio is taken.

公开(公告)号：JPH01237474A

公开(公告)日：1989-09-21

申请号：JP6347588

申请日：1988-03-18

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: G01R31/28

Abstract: PURPOSE:To enable the test of a circuit related to an input-output of a bus line without letting an excessive current flow, by a method wherein only data held in one set of data latch means are outputted to the bus line at the time of a scanning test. CONSTITUTION:FF circuits 1-3 which are data latch circuits have scanning function respectively. An output of the FF circuit 1 is supplied to a combination circuit 6 other than the FF circuits. Outputs of four FF circuits 2 in one set are supplied in parallel to four bus lines 9 through bus drive circuits 81-84 respectively. In the case when an ordinary operation is executed in such a circuit as having the above construction, a signal of 'L' level, for instance, is supplied to a bus control terminal 12. Thereby an output of the FF circuit 3 is selected in each of switching circuits 111-114 and a signal is supplied to the circuit 8 corresponding thereto. Thereby the outputs of the FF circuits 2 in four sets each comprising four of these circuits are outputted in parallel to the four bus lines 9 through the circuits 81-84 selected in accordance with the respective outputs of the FF circuits.

公开(公告)号：JPH01195378A

公开(公告)日：1989-08-07

申请号：JP1736288

申请日：1988-01-29

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: G01R31/26 ,  H03K19/00 ,  H03K19/0175

Abstract: PURPOSE:To eliminate the need of control terminals to reduce the number of external connection terminals by providing a clock state discriminating circuit part and a control gate part and outputting a signal corresponding to a DC test output set signal in the DC test state. CONSTITUTION:In the normal operation state where a clock signal (a pulse signal having first and second levels repeated) is inputted to an input terminal 67, a signal corresponding to the normal operation signal inputted to an input terminal 17 is outputted to an output terminal part 9. At the time of DC test, a first or second level signal corresponding to the DC test output set signal is outputted to the output terminal part 9 because an input terminal 75 is set to the potential in the first level (L=0) by a pull-up resistance 61. In this case, the clock signal is stopped and an input terminal 71 of an input-side inverter circuit part 63 is set to the second level (H=1) to perform the DC test of an integrated circuit.

公开(公告)号：JPS6214523A

公开(公告)日：1987-01-23

申请号：JP15341185

申请日：1985-07-12

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: H03K19/21

Abstract: PURPOSE:To attain a short delay time with a small number of elements by constituting a circuit with an inverter, a transfer gate, and a clocked inverter. CONSTITUTION:When an input signal A is '1', '0' and '1' are inputted to gates of transistors TRs Q15 and Q16 constituting a transfer gate 12 respectively and TRs Q15 and Q16 are turned off. Consequently, a signal B is blocked by the gate 12. However, a clocked inverter 14 is set to the operating state because TRs 12 and 13 are turned on together, and the signal B is inverted by the inverter 14. As the result, an inverted signal, the inverse of B is outputted from an output terminal. When the signal A is '0', TRs Q15 and Q16 are turned on together. Consequently, the signal B is transmitted to a connection point N10 through the gate 12. The inverter 14 is set to the non-operating state because TRs Q12 and Q13 are turned off together, and the signal B is blocked by the inverter 14. As the result, the signal B is outputted. When the signal B is '1' or '0', the signal A or, the inverse of A is outputted.

公开(公告)号：JPH0529381A

公开(公告)日：1993-02-05

申请号：JP17702691

申请日：1991-07-17

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI ,  TOTOKI TAKASHI

IPC: H01L21/60

Abstract: PURPOSE:To prevent, as much as possible, a latch up. CONSTITUTION:First bumps 3a are formed on the first surface 1a on which a semiconductor chip l is formed, and second bumps 3b are formed on a second surface 1b opposite to the first surface. First leads 6, to be bonded to the first bumps, are formed on one surface of a film carrier tape 4, whilst second leads 7, to be bonded to the second bumps, are formed on the other surface of the film carrier tape. The first bumps 3a and the first leads 6 are bonded together, and the second bumps 3b and the second leads 7 are bonded together.

公开(公告)号：JPH04250370A

公开(公告)日：1992-09-07

申请号：JP865291

申请日：1991-01-28

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI

IPC: G01R31/28 ,  G01R31/3185 ,  G11C7/10

Abstract: PURPOSE:To prevent an erronous operation without setting time limit for storing by storing test data and a test result in a first latch circuit which varies in the output impedance according to the input/output mode of a bidirectional input/output terminal. CONSTITUTION:A control signal T12 of H is input to an analog switch TG12 and is turned ON, and terminals D1 and D2 are connected together thereby. Mode signals MODE 1, 2 are also set by H at the same time, and the signal of L is output in common from NOR circuits 2, 4 which is input to a terminal E of first latch circuits L2, L4, and the output is of high impedance. In a test mode, a signal T12 of L is supplied to the switch TG12, and is turned OFF thereby, while the signals MODE 1, 2 are set by L and H respectively. The data for input/output mode setting is input from an input terminal SIM to fourth latch circuits L5 and L7 and is stored therein. A clock signal supplied to third latch circuits L6, L8 through terminals G6, G8 is retained by L, and the data retaining condition is thus maintained.