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    Charging/discharging circuit and binarizing circuit
    1.
    发明专利
    Charging/discharging circuit and binarizing circuit 审中-公开
    充电/放电电路和二极管电路

    公开(公告)号：JP2009253306A

    公开(公告)日：2009-10-29

    申请号：JP2008094599

    申请日：2008-04-01

    Applicant: Toshiba Corp ,  Toshiba Information Systems (Japan) Corp ,  Toshiba Joho System Technology Kk ,  東芝情報システムテクノロジー株式会社 ,  東芝情報システム株式会社 ,  株式会社東芝

    Inventor： HONMA SOICHI ,  SUZUKI TSUNEO ,  YAMAMOTO TATSUYA

    IPC: H03K5/08 ,  H03K5/1532 ,  H04L25/03 ,  H04L27/06

    Abstract: PROBLEM TO BE SOLVED: To provide a charging/discharging circuit and a binarizing circuit, capable of keeping the amplitude of an input signal compared to a binary threshold value constant even in demodulating an ASK (amplitude shift keying) signal using RSSI (received signal strength indicator). SOLUTION: An ASK signal demodulated by an RSSI detector 17 is inputted into a peak hold circuit 23, the peak hold circuit 23 detects a peak value of an input signal inputted into a charging/discharging section 24, a clip circuit 22 clips a level not higher than a given value, from the peak value of the input signal inputted into the charging/discharging section 24, and the charging/discharging section 24 rapidly charges and discharges a capacitor C2 using the signal clipped in the clip circuit 22, thereby generating a reference voltage Vref used as a threshold value of a comparator 27. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种充电/放电电路和二值化电路，即使在使用RSSI解调ASK（振幅移动键控）信号时，也能够将输入信号的幅度与二进制阈值相比恒定， 接收信号强度指示）。 解决方案：由RSSI检测器17解调的ASK信号被输入到峰值保持电路23中，峰值保持电路23检测输入到充电/放电部分24的输入信号的峰值，钳位电路22剪辑 从输入到充电/放电部分24的输入信号的峰值以及充电/放电部分24中的电平不会高于给定值的电平，并且使用夹在电路22中的信号快速地对电容器C2进行充电和放电， 从而产生用作比较器27的阈值的参考电压Vref。（C）2010，JPO＆INPIT

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：JP2003100811A

    公开(公告)日：2003-04-04

    申请号：JP2001298253

    申请日：2001-09-27

    Applicant: TOSHIBA CORP

    Inventor： HONMA SOICHI

    IPC: H01L23/29 ,  H01L21/60 ,  H01L23/31

    Abstract: PROBLEM TO BE SOLVED: To increase connection strength for improving reliability in a semiconductor device where a semiconductor element is connected to a wiring board via a metal bump. SOLUTION: In the semiconductor device, at the periphery of a solder bump 5 for connecting an electrode pad 4 of a semiconductor chip 3 to a wiring pad 2 of a wiring board 1, a first resin layer 6 is formed and has a fillet between the solder bump 1 and the wiring board 1. Such a bump junction and the first resin layer 6 are formed by aligning the solder bump 5 and the wiring pad 2 of the wiring board 1 for fixing temporarily to heat and joint them after a layer made of a resin containing flux constituent is formed by a squeegeeing system at the outer periphery of the solder bump 5 of the semiconductor chip 3. Then, the resin containing flux constituent layer is cured, thus forming the fillet-like first resin layer 6.

    Semiconductor device and its manufacturing method
    4.
    发明专利
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：JP2003077930A

    公开(公告)日：2003-03-14

    申请号：JP2001268871

    申请日：2001-09-05

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： HONMA SOICHI ,  SUGIYAMA TORU ,  MORITSUKA KOHEI

    IPC: H01L21/331 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/52 ,  H01L29/737

    CPC classification number: H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device where heat dissipating characteristics can be improved without the occurrence of element breakdown and bump electrodes can be easily microfabricated, and to provide its manufacturing method. SOLUTION: In the semiconductor device 1, an emitter electrode 31 is arranged on an emitter region 26 of a heterojunction bipolar transistor 20 of a compound semiconductor element 2, and an emitter main electrode terminal 42A is connected to the emitter electrode 31 through an opening 41A of an interlayer dielectric 40. A film thickness of the emitter main electrode terminal 42A is thick in comparison with that of the emitter electrode 31. The interlayer dielectric 40 includes at least an organic film, and the film thickness of the interlayer dielectric 40 is equivalent to that of the emitter main electrode terminal 42A. An Au stud bump electrode 43A is arranged on the emitter main electrode terminal 42A.

    Abstract translation: 要解决的问题：提供一种半导体器件，其中可以提高散热特性，而不会发生元件击穿，并且凸块电极可以容易地微制造，并提供其制造方法。 解决方案：在半导体器件1中，发射极31配置在化合物半导体元件2的异质结双极晶体管20的发射极区域26上，发射极主电极端子42A通过开口41A与发射电极31连接 发射极主电极端子42A的膜厚与发射电极31的膜厚相比较厚。层间电介质40至少包含有机膜，并且层间电介质40的膜厚等于 与发射极主电极端子42A的距离。 在发射极主电极端子42A上配置Au凸块电极43A。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明专利
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效

    公开(公告)号：JP2002076045A

    公开(公告)日：2002-03-15

    申请号：JP2000260283

    申请日：2000-08-30

    Applicant: TOSHIBA CORP

    Inventor： HONMA SOICHI

    IPC: H01L21/60

    Abstract: PROBLEM TO BE SOLVED: To provide a high reliable semiconductor integrated circuit device which have no fear for cracking of the semiconductor substrate when the semiconductor integrated circuit device is mounted on a circuit board. SOLUTION: The semiconductor substrate 2 of the semiconductor integrated circuit device in this invention is formed into a square having a main plane, and sides 2a and 2b which are parallel to a cleavage plane, and sides 3a and 3b which orthogonally intersect the cleavage plane. A plurality of bump electrodes 8 are placed on the main plane along each side of the semiconductor substrate 2. The number of bump electrodes 8 placed along the edges 3a and 3b which orthogonally intersect the above cleavage plane is greater than that of the bump electrodes 8 which are placed along the edges 2a and 2b parallel to the above cleavage plane.

    SEMICONDUCTOR AND ITS MANUFACTURE
    7.
    发明专利
    SEMICONDUCTOR AND ITS MANUFACTURE 失效

    公开(公告)号：JPH0936120A

    公开(公告)日：1997-02-07

    申请号：JP18044095

    申请日：1995-07-17

    Applicant: TOSHIBA CORP

    Inventor： YAMADA HIROSHI ,  HONMA SOICHI ,  SAITO MASAYUKI

    IPC: H01L21/60 ,  H01L21/321

    Abstract: PROBLEM TO BE SOLVED: To prevent the diffusion of solder and barrier metal and to specifically form the structure of a bump electrode by a method wherein the first connection layer, formed on the barrier metal layer on a bonding pad, and the solder bump, which is formed on the second connection layer, are contained in the semiconductor device. SOLUTION: A semiconductor chip 1, the bonding pad 7 provided on the semiconductor chip 1, a barrier metal layer 2 to be formed on the bonding pad 7, and the first connection layer 4, which is brought into the state of stabilized alloy with the barrier metal layer 2 and solder bump material, are formed. The semiconductor device is fundamentally composed of the second connection layer 5, containing high density of metal which is not stably alloyed with the barrier metal layer 2 among solder bump materials and stably alloyed with the first connection layer, and the solder bump 3 formed on the second connection layer. As a result, the lowering of connection strength caused by the diffusion of metal can be prevented.

    Semiconductor device
    8.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2014179429A

    公开(公告)日：2014-09-25

    申请号：JP2013051947

    申请日：2013-03-14

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： HONMA SOICHI ,  MATSUURA EIGO ,  SHIMA SHINYA ,  MUKODA HIDEKO ,  AOKI HIDEO

    IPC: H01L23/12

    CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which does not cause breaking even in TCT (Temperature Cycle Test) to ensure high reliability.SOLUTION: A semiconductor device comprises: a semiconductor chip 1; a first resin 2 for burying the semiconductor chip 1 so as to expose a surface of the semiconductor chip 1; a second resin 3 formed on a surface of the first resin 2, which lies in the same plane with the surface of the semiconductor chip 1; a re-wiring layer 4 which is formed on the second resin 3 and electrically connected to the semiconductor chip 1; an external connection terminal 5 formed on a wiring layer 4; and a metal plate 6 formed on an opposite side surface of the first resin 2, which is opposite to the surface where the semiconductor chip 1 is buried, in which the first resin 2 has an elastic modulus of 0.5-5 GPa.

    Abstract translation: 要解决的问题：提供即使在TCT（温度循环测试）中也不会引起断裂的半导体器件，以确保高可靠性。解决方案：半导体器件包括：半导体芯片1; 用于掩埋半导体芯片1以露出半导体芯片1的表面的第一树脂2; 形成在与半导体芯片1的表面位于同一平面上的第一树脂2的表面上的第二树脂3; 形成在第二树脂3上并与半导体芯片1电连接的再布线层4; 形成在布线层4上的外部连接端子5; 以及金属板6，其形成在第一树脂2的相对于半导体芯片1埋入的表面的相对侧表面上，其中第一树脂2具有0.5-5GPa的弹性模量。

    Semiconductor device and manufacturing method of the same
    9.
    发明专利
    Semiconductor device and manufacturing method of the same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：JP2013211427A

    公开(公告)日：2013-10-10

    申请号：JP2012080944

    申请日：2012-03-30

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： SHIMA SHINYA ,  HONMA SOICHI

    IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522

    CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which improves reliability and productivity by inhibiting deterioration in insulation reliability and the like, which is caused based on variation in a depth direction of a reformed region of an insulation resin layer.SOLUTION: A semiconductor device of an embodiment comprises: an insulation resin layer 5 which is provided on a semiconductor substrate 2 having a first wiring layer 3 and which has an opening 6 for exposing a part of the first wiring layer 3; and a second wiring layer 7 provided on the insulation resin layer 5. The second wiring layer 7 is composed of an electroless metal plating film. The insulation resin layer 5 includes a laminated film of a first resin layer 10 and a second resin layer 12. The electroless metal plating film has an anchor layer 14 generated by immersion of plated metal into the insulation resin layer 5. The anchor layer 14 is formed only in the second resin layer 11.

    Abstract translation: 要解决的问题：提供一种半导体器件，其通过抑制由绝缘树脂层的重整区域的深度方向的变化引起的绝缘可靠性等的劣化来提高可靠性和生产率。解决方案：半导体器件 实施例包括：绝缘树脂层5，其设置在具有第一布线层3的半导体基板2上，并且具有用于暴露第一布线层3的一部分的开口6; 以及设置在绝缘树脂层5上的第二布线层7.第二布线层7由化学镀金属膜构成。 绝缘树脂层5包括第一树脂层10和第二树脂层12的层叠膜。无电解金属镀膜具有通过将电镀金属浸渍到绝缘树脂层5中而产生的锚定层14.锚层14是 仅形成在第二树脂层11中。

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