公开(公告)号：JPH09311344A

公开(公告)日：1997-12-02

申请号：JP6130097

申请日：1997-03-14

Applicant: TOSHIBA CORP

Inventor： IIDA ATSUKO ,  KONNO AKIRA ,  SAITO MASAYUKI ,  MORI MIKI ,  FUKUDA YUMI ,  UCHIDA TATSUAKI ,  MIYAGI TAKESHI ,  KIZAKI YUKIO ,  ATSUTA MASAKI

IPC: G02F1/1339 ,  G02F1/13 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1347 ,  G09F9/30

Abstract: PROBLEM TO BE SOLVED: To utterly eliminate existence of a non-display area on a display screen or to make it minimum by arranging plural array substrates so that display areas of respective array substrate edge parts face to both surfaces of a counter substrate on whose both surfaces common electrodes arc respectively formed with each other across the counter substrate. SOLUTION: This device is provided with a counter substrate 23 in which common electrodes 22 are respectively formed on both surface of a translucent substrate 21 and plural array substrates 26a, 26b in which semiconductor elements and signal lines 25 are formed on a translucent substrate 24. Respective array substrates 26a, 26b are arranged so that display areas of respective substrate edge parts face to both surfaces of the counter substrate 23 with each other across the substrate 23. In short, respective array substrates 26a 26b are arranged in an adjacent relation so that one parts of the display areas of the array substrate edge parts are overlapped with each other across the counter substrate 23 while being faced to the both surfaces of the counter substrate 23. Liquid crystals 29a, 29b are sealed in spaces among the counter substrate 23 and respective array substrates 26a, 26b.

公开(公告)号：JPH09172234A

公开(公告)日：1997-06-30

申请号：JP32914095

申请日：1995-12-18

Applicant: TOSHIBA CORP

Inventor： MIYAGI TAKESHI ,  SAITO MASAYUKI

IPC: H05K1/03

Abstract: PROBLEM TO BE SOLVED: To form a wiring board having a BCB insulating film precisely patterned on a printed board, by a method wherein a UV ray absorbing layer is formed on a board, and absorbs UV ray casted on a benzocyclobutene(BCB) film to prevent the UV ray from entering the board. SOLUTION: An UV ray absorbing film 3 and a benzocyclobutene film 2 are previously formed on a printed board 1. When the board 1 is irradiated with UV ray via glass masks 4, 5, only the benzocyclobutene film 2 in a specified area is exposed to light. Thereby the benzocyclobutene film 2 to be obtained is formed only in a specific area, and does not extend to the other area. When a wiring layer is laminated on the benzocyclobutene film 2, a wiring board which has the precisely patterned BCB insulating film 2 excellent in electric characteristics on a printed board 1 can be obtained.

公开(公告)号：JPH0992651A

公开(公告)日：1997-04-04

申请号：JP24953495

申请日：1995-09-27

Applicant: TOSHIBA CORP

Inventor： MIZUSAWA YUMI ,  TAKAGI AYAKO ,  SAITO MASAYUKI

IPC: G02F1/136 ,  H01L21/321 ,  H01L21/60 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To provide a reliable semiconductor element easy to repair and its connection method. SOLUTION: A bump electrode 2 is made up of a signal bump electrode 21 mainly effective in electrical connection and a fixing bump electrode 22 mainly effective in mechanical connection. In a continuity test for a semiconductor element 1, only the fixing bump electrode 22 is joined with a wiring pattern in a solid-phase diffusion state. After the continuity test, the signal bump electrode 21 is also joined with the wiring pattern in a solid-phase diffusion state. When the semiconductor device 1 is repaired, damage to a position of wiring pattern to be joined with the signal bump electrode 21 is prevented, and even when the repair is repeated, reliability in a bump electrode 2 is not reduced.

公开(公告)号：JPH0982760A

公开(公告)日：1997-03-28

申请号：JP17041296

申请日：1996-06-28

Applicant: TOSHIBA CORP

Inventor： SHIZUKI YASUSHI ,  IZEKI YUJI ,  YOSHIHARA KUNIO ,  YAMADA HIROSHI ,  SAITO MASAYUKI ,  ONO NAOKO ,  TATEYAMA KAZUKI

IPC: G01R31/04 ,  H01L21/60 ,  H01L21/66 ,  H01L23/485 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

Abstract: PROBLEM TO BE SOLVED: To make it possible to mount a semiconductor device at a high density and to obtain the device having excellent reliability by providing solder resist so formed as to surround a semiconductor element at a predetermined distance on a circuit board. SOLUTION: The semiconductor device comprises a circuit board 13 having a plurality of pad electrodes 14, a semiconductor element 11 mounted thereon, and solder resist 17 so formed as to surround the element 11 at a predetermined distance. Further, the device comprises a plurality of terminal electrodes 12 provided at the end of the element 11, a gap provided between the board 13 and the element 11, and a plurality of solder bumps 15 for connecting the electrodes 14 to the electrodes 12. The electrode 14 includes the part extended from the lower part of the electrode 12 of the element 11 to the resist 17 at the outside of the element 11. The bump 15 has the part 151 extended onto the part extended to the outside of the element 11 of the electrode 14.

公开(公告)号：JPH0936120A

公开(公告)日：1997-02-07

申请号：JP18044095

申请日：1995-07-17

Applicant: TOSHIBA CORP

Inventor： YAMADA HIROSHI ,  HONMA SOICHI ,  SAITO MASAYUKI

IPC: H01L21/60 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To prevent the diffusion of solder and barrier metal and to specifically form the structure of a bump electrode by a method wherein the first connection layer, formed on the barrier metal layer on a bonding pad, and the solder bump, which is formed on the second connection layer, are contained in the semiconductor device. SOLUTION: A semiconductor chip 1, the bonding pad 7 provided on the semiconductor chip 1, a barrier metal layer 2 to be formed on the bonding pad 7, and the first connection layer 4, which is brought into the state of stabilized alloy with the barrier metal layer 2 and solder bump material, are formed. The semiconductor device is fundamentally composed of the second connection layer 5, containing high density of metal which is not stably alloyed with the barrier metal layer 2 among solder bump materials and stably alloyed with the first connection layer, and the solder bump 3 formed on the second connection layer. As a result, the lowering of connection strength caused by the diffusion of metal can be prevented.

公开(公告)号：JPH0837254A

公开(公告)日：1996-02-06

申请号：JP17132094

申请日：1994-07-22

Applicant: TOSHIBA CORP

Inventor： EBITANI TAKASHI ,  SHIMIZU SEISABURO ,  UCHIDA TATSUAKI ,  SAITO MASAYUKI ,  TOGASAKI TAKASHI ,  KIZAKI YUKIO ,  MORI MIKI

IPC: H01L23/12 ,  H01L21/60 ,  H05K1/18 ,  H05K3/34 ,  H01L21/321

Abstract: PURPOSE:To secure the height of a bump by a method wherein the bump is composed of the first metal, which is fused at a mounting temperature, and the second metal having a melting point higher than that of the first metal. CONSTITUTION:A bump 9, which connects the pad electrode 3 of a wiring substrate 2 and the pad electrode 5 of a circuit part 4, is composed of the first low melting point metal layer 6, a high melting point metal layer 7 which as a core, and the second low melting point metal layer 8. Besides, the second low melting point metal layer 8 may be composed of the material different from the first low melting point metal layer 6, and the material which is fused at mounting temperature is used. Moreover, the thickness of the high melting point metal layer 7 in the bump is made thinner than the thickness of other part. Also, the cross section of the high melting point metal layer 7 is made smaller than the cross section of the pad electrodes 3 and 5. As a result, a highly reliable electronic circuit device can be obtained easily.

公开(公告)号：JPH07235565A

公开(公告)日：1995-09-05

申请号：JP2523394

申请日：1994-02-23

Applicant: TOSHIBA CORP

Inventor： EBITANI TAKASHI ,  MORI MIKI ,  UCHIDA TATSUAKI ,  TOGASAKI TAKASHI ,  KIZAKI YUKIO ,  SAITO MASAYUKI

IPC: H01L21/60 ,  H01L23/12 ,  H05K3/34

Abstract: PURPOSE:To enable mounting a package constituted of a module substrate and insulator via bumps without using a paticular bump forming method, by dispersing solid fine particles in the bumps which particles control the height of the bumps. CONSTITUTION:In the connection wiring of a wiring board 2 and a package 18, circuit components electrically connected with the wiring board 2 via bumps 4 are arranged on the wiring board 2, and solid fine particles 30 are dispersed in the bumps 4 which particles control the height of the bumps 4. The solid fine particles come into contact with each other, and the rolling phenomenon can be evaded. The height of the bumps can be controlled by changing the mixing ratio. When a package 18 or the like constituted of a module substrate and insulator is mounted on the wiring board 2, high bumps 4 can be easily formed.

公开(公告)号：JPH0758201A

公开(公告)日：1995-03-03

申请号：JP20233093

申请日：1993-08-16

Applicant: TOSHIBA CORP

Inventor： HIGUCHI KAZUTO ,  YAMADA HIROSHI ,  SAITO MASAYUKI

IPC: H01L21/3205 ,  H01L21/768 ,  H05K3/40 ,  H05K3/46

Abstract: PURPOSE:To obtain a highly reliable multilayer wiring which can be brought into the state of high density easily by a method wherein, after a contact hole is formed in the insulating film of a board and flat surface is obtained by plating, a wiring layer is formed in such a manner that it is brought into contact with the flat surface. CONSTITUTION:A copper thin film pattern is formed on the insulating film 2 formed on the surface of a board 1 as the first layer wiring film 3. Photosensitive polyimide is coated thereon, and after a contact hole 9, with a side of about 20mum, has been formed by conducting an exposing and developing operation, a heat treatment is conducted at 400 deg.C for thirty minutes, and an interlayer insulating film 4 is formed. Then, after forming a titanium film 5 and a copper film 6 successively in 1mum thickness using a sputtering method, a thick copper- plating film 7 is formed on a recessed part by conducting electric plating under the condition wherein a flat surface can be obtained using the above-mentioned titanium film 5 and copper film 6 as an electrode. A titanium-copper-titanium multilayer thin film 8 is formed on the board 1 for which burying is conducted as the second wiring layer. As a result, a highly precise multilayer wiring can be obtained by reduced manhours.

公开(公告)号：JPH05235102A

公开(公告)日：1993-09-10

申请号：JP3902892

申请日：1992-02-26

Applicant: TOSHIBA CORP

Inventor： YAMADA HIROSHI ,  SAITO MASAYUKI

IPC: H01L21/60 ,  H01L21/321

Abstract: PURPOSE:To realize a semiconductor device wherein its heatdissipating property and its electric conductivity are excellent and its reliability is high with reference to a heat stress by a method wherein a bump connection part at the semiconductor device is constituted of a first material whose heat conductivity and electric conductivity are good and whose melting point is high and of a second material whose melting point is low and to realize its manufacturing method. CONSTITUTION:In a semiconductor device in which a semiconductor element 1 is connected in a facedown manner, a bump structure in which the circumference of a mushroom-shaped metal has been covered with a low-melting-point metal is formed around the mushroom-shaped metal where a part in which a wiring board 8 whose electric conductivity is excellent comes into contact with electrodes 9 has been flattened. Thereby, the semiconductor device whose heat-dissipating property is excellent, whose connection strength is high, whose heat stress and humidity-resistant degree are excellent, whose reliability is high and which can be made thin can be obtained by a simple method.

公开(公告)号：JPH0555301A

公开(公告)日：1993-03-05

申请号：JP21362091

申请日：1991-08-26

Applicant: TOSHIBA CORP

Inventor： YAMAMOTO YOSHIE ,  MOTOMIYA AKINORI ,  SAITO MASAYUKI

IPC: H01L21/60

Abstract: PURPOSE:To provide an electronic circuit device on which electronic parts can be face-down mounted on a wiring substrate without forming a bump electrode on the electronic parts such as an IC chip and the like, and to cut down the manufacturing cost. CONSTITUTION:In an electronic circuit device on which an IC chip 20 is face- down mounted on a wiring substrate 10, after a conductive layer 12, consisting of a thermoplastic resin composition, has been formed in a prescribed pattern on an insulating layer 11 consisting of a thermoplastic composition, an insulating layer 13, consisting of a thermoplastic resin composition and having an opening on a part of the conductive layer 12, is formed on the insulating layer 11 and the conductive layer 12. Then, a wiring substrate 10, on which the conductive layer 12 is exposed on the main surface on the side of an insulating layer 13 by pressing the layers 11 to 13 to the direction of lamination, is formed. Subsequently, an IC chip 20 is mounted on the wiring substrate 10 is such a manner that the electrode surface 21 is mated to the conductive layer 12 exposed to the above-mentioned main surface, and then the IC chip 20 is pressure-welded by heat to the wiring substrate 10.