公开(公告)号：JPS63215213A

公开(公告)日：1988-09-07

申请号：JP4946687

申请日：1987-03-04

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI

IPC: H03K5/13 ,  H03K5/131 ,  H03K5/26 ,  H03L7/00 ,  H03L7/06 ,  H03M1/12

Abstract: PURPOSE:To simplify and miniaturize the circuit constitution by providing a phase comparison circuit extracting a phase error quantity, a deciding circuit expressing an optimum sample, an averaging circuit averaging a deciding circuit output signal for each value of log2N (N is a sampling number) bit each and a phase control circuit. CONSTITUTION:Four sample clocks have phases of 0, pi/2, pi, 3pi/2 with respect to the phase of a reference clock. Suppose that control information and a tentative decision output are coincident, the control information is divided into eight by the MSB and the LSB at each phase region. With the MSBh and the LSBi located at '0', '0', it is discriminated that the phase of the optimum reference clock exists at the region of the phase '0' and with the phase of the optimum reference clock exists at '1', '0', it is discriminated that the optimum reference clock exists at the region of the phase pi. With the MSBh and the LSBi located at '1', '1' and '0', '1', the phase depends on shift information (j) and with the shift information (j) at logical '1' and the MSBh and the LSBi at '1', '0', '1', the phase is shifted by pi/4 to the left. As a result, the new reference clock phase (f) is shifted to a region where the MSBh and the LSBi are placed at '0', '0'.

公开(公告)号：JPS6342240A

公开(公告)日：1988-02-23

申请号：JP18423286

申请日：1986-08-07

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI ,  SUZUKI HIDEO

IPC: H04L7/033 ,  H03L7/08 ,  H03L7/085 ,  H04L7/02

Abstract: PURPOSE:To execute a high speed timing synchronization and a high speed pulling-in by generating a complex signal in which one of an input signal and a delay signal, land the other are allowed to correspond to a real number part and an imaginary number part, respectively, and using a signal obtained by its complex square, as a phase comparing signal. CONSTITUTION:With respect to an input signal (a), a' is generated by a delaying circuit 11, and a complex signal (a + ja') is formed by the output a' and the input signal (a), and supplied to a complex arithmetic circuit 13. In the complex arithmetic circuit 13, a first phase comparing signal aa', and a second phase comparing signal a -a' are obtained as outputs. A detecting circuit 15 and a control circuit 17 prevent the error detection of a phase error generatd by the continuation of the same code, and extract only a correct phase error as the first phase comparing signal. Also, the first phase comparing signal and the second phase comparing signal are utilized for stationary slow phase control, and for a control for an initial high speed pulling-in.

公开(公告)号：JPH01268321A

公开(公告)日：1989-10-26

申请号：JP9566688

申请日：1988-04-20

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI ,  NAKAMURA MAKOTO

IPC: H04J4/00 ,  H04B7/15 ,  H04B7/208

Abstract: PURPOSE:To simultaneously use two or more terminal equipments in one earth station by providing a first modulating circuit for executing a modulation output by changing a transmission frequency band, and a second demodulating circuit for executing a demodulation by changing a demodulation synchronizing speed. CONSTITUTION:A signal from an earth station 1 which has passed through a communication satellite 3 is received by a central control station 2, and a receiving signal is demodulated by a second demodulating circuit 22. When a line control circuit 25 receives a calling signal from other terminal equipment 11b than, for instance, a terminal equipment 11a in the earth station 1 being in the course of communication already, a synchronizing speed control circuit 32 leads out a demodulation synchronizing speed signal of two times and generates a line allocating signal so as to supply said signal to the second demodulating circuit 22. The first control signal extracting circuit 14 of the earth station 1 extracts the line allocating signal from in the demodulating signal and supplies it to the first modulating circuit and a modulation frequency band is doubled. In such a way, plural terminal equipments can be operated simultaneously without raising the transmission power.

公开(公告)号：JPH01228354A

公开(公告)日：1989-09-12

申请号：JP5361988

申请日：1988-03-09

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI

IPC: H04L27/22

Abstract: PURPOSE:To simply eliminate an ambiguity by bringing base band signal of two systems which have been reproduced to differential operation at every system and setting them to two kinds of ambiguities. CONSTITUTION:In a receiver 2, a synchronous detection circuit 7 establishes firmly a synchronization of a carrier wave and a bit discriminating clock from a four-phase PSK modulating signal which has been received, and reproduces base band signals I', Q' of two systems. Two differential operation circuits 8, 9 convert every system of the base band signals I', Q' to differential signals for obtaining an absolute value of a soft decided value difference. As a result, an ambiguity by a carrier wave reproducing phase of the differential signals of two systems can be limited to two kinds of I and Q of the same phase and Q and I of the opposite phase against convolution signals I, Q of two systems of a transmitter 1. A selecting circuit 10 selects by a selecting signal whether the differential signals of two systems inputted to an error correcting circuit 11 are set to the same phase or the opposite phase.

公开(公告)号：JPS6313417A

公开(公告)日：1988-01-20

申请号：JP15499486

申请日：1986-07-03

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI

IPC: H03K5/26 ,  G01R25/00 ,  H03L7/08 ,  H03L7/085

Abstract: PURPOSE:To output a phase error always constant by providing a means extracting phase information, a means generating a control signal and a means controlling a phase error detection gain so as to select and output complex phase error information. CONSTITUTION:The titled circuit consists of a means extracting complex phase error information c1, c2, c3, c4, d1, d2, d3, d4, f, g with respect to specific frequencies among a received signal depending on plural phase error detection gains, a means selecting and outputting plural complex phase error information c1-c4, d1-d4 and a means detecting a level fluctuation of an output signal and generating a control signal. The fluctuation of selected output level is detected, high- order bit complex phase error information c1-c4, d1-d4 with a small detection gain are selected and outputted in case of a large level, and low-order bit complex phase error information c1-c4, d1-d4 with a large detection gain are selected and outputted in case of a small level to obtain a stable phase error (h). Thus, even with a mean extraction level fluctuated, the phase error (h) is detected without any error.

公开(公告)号：JPS62224137A

公开(公告)日：1987-10-02

申请号：JP6586786

申请日：1986-03-26

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI ,  SUZUKI HIDEO

IPC: H03K5/00 ,  H03K5/26 ,  H04L7/02

Abstract: PURPOSE:To attain a fast phase locking by deciding a detected phase at plural regions and changing the phase of a reference timing signal based on the result so as to eliminate the increase in the detection error caused at the phase error of nearly + or -pi. CONSTITUTION:The 1st recovery timing signal 2 is retarded by 1/2 of the transmission rate at the 2nd delay circuit 17 to generate a comparison signal 18, which is compared with the 1st transmission rate frequency component 5 at the 2nd latch circuit 16 to apply phase decision. The phase decision signal 13 switches the phase of the 1st recovery timing signal 2 in an EX-OR circuit 15 to generate the 2nd recovery timing signal 14. A demodulated base band signal 1 is inputted to the 1st latch circuit 9 and the 2nd recovery timing signal 14 extracts the 2nd transmission rate frequency component 6 including the phase error information and the recovered base band signal 4. A substraction circuit 12 subtracts the 2nd transmission rate frequency component 6 from the 1st transmission rate frequency component 5 to extract a phase error signal 7.

公开(公告)号：JPS6162258A

公开(公告)日：1986-03-31

申请号：JP18386184

申请日：1984-09-04

Applicant: Nippon Telegr & Teleph Corp ,  Toshiba Corp

Inventor： KORI TAKEJI ,  SUZUKI HIDEO ,  KUDO KYOICHI

IPC: H04L7/00 ,  H04L7/033 ,  H04L7/06

CPC classification number: H04L7/00

Abstract: PURPOSE:To obtain correct phase information even when a change is caused in an input signal by the pattern and variation occurs in amplitude value by removing amplitude information from a set of orthogonal timing information and obtained a value according to phase information. CONSTITUTION:Each set of orthogonal 2 signals of orthogonal filters 15a, 15b are added by the first and second adders 20a, 21b and subtracted by the first and second subtracters 27a, 27b and a new set of independent signals are made. Then, such orthogonal timing information is supplied to a converting tape 7 and phase error is determined primarily and theoretically according to the ratio A/B of a signal A from the third adder 23 to a signal B from the fourth adder 25. Accordingly, a phase error signal is set according to the phase error.

Abstract translation: 目的：为了获得正确的相位信息，即使当通过模式在输入信号中引起改变时，通过从一组正交定时信息中移除振幅信息并且根据相位信息获得值，从而在振幅值中发生变化。 构成：正交滤波器15a，15b的每组正交2信号由第一和第二加法器20a，21b相加，并被第一和第二减法器27a，27b相减，并且进行一组新的独立信号。 然后，这样的正交定时信息被提供给转换带7，并且根据从第三加法器23的信号A到第四加法器25的信号B的比率A / B，主要和理论地确定相位误差。因此， 相位误差信号根据相位误差设定。

公开(公告)号：JPH10144094A

公开(公告)日：1998-05-29

申请号：JP29176496

申请日：1996-11-01

Applicant: TOSHIBA CORP

Inventor： KUDO KYOICHI

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/42

Abstract: PROBLEM TO BE SOLVED: To obtain normal information without exchanging an integrated circuit by performing readouts as to lines on which the same cells are arranged each other in an orthogonal direction, discoving faulty cells based on read-out data and modifying them to correct data. SOLUTION: This storage integrated circuit is provided with a storage circuit 10, a row address decoder (LD) 20, a first column address decoder (CD) 30, a second CD 40, a parity decision part 70 and an error correction part 80. The LD 20 obtains a row address from address data with respect to the storage circuit 10. The CD 30 decodes a column address among the address data to select either of first bit lines. The CD 40 decodes a column address at the point of time when the row address is not activated among the address data to select either of second word lines. The parity decision part 70 discovers an error based on the signal noncoincidence between first and second bit lines and the error correction part 80 outputs output data after modifying the output data based on the result of the decision part.

公开(公告)号：JPS62136935A

公开(公告)日：1987-06-19

申请号：JP27754785

申请日：1985-12-10

Applicant: TOSHIBA CORP

Inventor： SERIZAWA MUTSUMI ,  KUDO KYOICHI

IPC: H04N7/08 ,  H04J3/06 ,  H04L7/10 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/081 ,  H04N7/083 ,  H04N7/087 ,  H04N7/088

Abstract: PURPOSE:To attain high speed synchronization establishment by shifting the phase of a recovery clock signal by a quantity corresponding to a phase difference with a clock signal recovered from a burst signal received just before at every time a new burst signal is received. CONSTITUTION:A phase difference DELTAphid between recovery clock signals recovered from a burst signal from both stations A, B is stored in a storage circuit 7, and just after a burst signal from the station A is received, the recep tion of the burst signal from the station B is forecast or known in advance, then the phase difference DELTAphid information is read and fed to a phase shifter 4 from the storage circuit 7 just before the burst signal from the station B is received. Thus, the recovery clock signal outputted from a VCO 3 is phase- shifted by DELTAphid and the recovery clock is nearly synchronized with CBP=cos(omegaAt +DELTAphiA-DELTAphid)=cos(omegaBt+DELTAphiB'), where DELTAphiB DELTAphiB'. Thus, the synchronization of the clock recovery circuit is established in a very short time.

公开(公告)号：JPS61257021A

公开(公告)日：1986-11-14

申请号：JP9902985

申请日：1985-05-10

Applicant: TOSHIBA CORP

Inventor： SERIZAWA MUTSUMI ,  KUDO KYOICHI

IPC: H03L7/085 ,  H03L7/08 ,  H03L7/087 ,  H04L7/02 ,  H04L7/033

Abstract: PURPOSE:To obtain a phase locked circuit with excellent noise resistance by smoothing outputs of the 1st and 2nd comparators having different phase comparison characteristics and then synthesizing them so as to generate a control signal controlling a VCO. CONSTITUTION:A modulation signal subject to modulation such as phase modulation or frequency modulation is inputted to an input terminal 1 as the 1st signal. The signal 11 is given to the 1st and 2nd phase comparators 3, 4, the phase is compared with the 2nd signal 12 whose phase controlled from a voltage controlled oscillator VCO 2. The comparator 3 has a sawtooth wave phase comparison characteristic and the comparator 4 has a triangle wave phase comparison characteristic. The output signals of the comparators 3, 4 are smoothed by loop filters 5, 6 being smoothing means, a noise component is eliminated and the result is fed to a control signal generating circuit 7. The circuit 7 synthesizes output signals of the filters 5, 6 and generates a control signal 13 to control the VCO 2.