公开(公告)号：JPH05183531A

公开(公告)日：1993-07-23

申请号：JP34658491

申请日：1991-12-27

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H04J3/00 ,  H04J3/12

Abstract: PURPOSE:To provide the multiplex signal transmission able to send signals of two kinds or more while keeping the utilizing efficiency of a frequency high by detecting an error of a signal sent with a 2nd error detection code with higher reliability than that of a 1st error detection code. CONSTITUTION:A signal received through a transmission line to a terminal 204 is converted into a signal at a base band by a demodulator 60. A packet decomposing circuit 70 detects the synchronizing signal from the signal at the base band and extracts a coding signal S104. The coded signal S104 is stored once in a buffer 90. A reception signal discrimination circuit 80 uses a 2nd CRC signal and whether the coded signal S104 is a digitized voice signal or a control signal is discriminated. The received coding signal S104 is divided by a generation polynomial, its residue is obtained and when the residue is zero, the signal is discriminated to be the control signal and when the residue is not zero, the signal is discriminated to be the digital voice signal.

公开(公告)号：JPH05175940A

公开(公告)日：1993-07-13

申请号：JP34350891

申请日：1991-12-25

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H03M13/00 ,  H04L1/00

Abstract: PURPOSE:To obtain a decoding signal with high reliability by spreading an error detection coding signal into an error correction code word so as to implement error correction coding, sending the result, selecting plural objects of decode words at a receiver side thereby discriminating the presence of an error. CONSTITUTION:An inputted information signal is coded by an error detection code, the coded signal is divided into m-sets of signals and subject to error correction coding, and the result is sent. A demodulator 5 demodulates the signal at a receiver side, an error correction decoding circuit 6 selects plural objects of the code word with respect to m-sets of error correction coding signals and they are stored in buffers 71-7m. Then the buffers 71-7m select an object signal by a command from a decoding-object selection circuit 9 and outputs the selected signal to an error detection circuit 8. The circuit 8 discriminates the presence of an error due to an error detection code and outputs a signal of a set in which no error is detected as decoding information. Thus, the reception signal is decoded with high reliability.

公开(公告)号：JPH05122163A

公开(公告)日：1993-05-18

申请号：JP28026391

申请日：1991-10-28

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H04B14/04

Abstract: PURPOSE:To highly efficiently transmit a multiplex signal without adding an identification(ID) signal to a transmitting signal by detecting the existence of an error based upon an error detecting signal added to a sound signal and deciding a sound signal at the time of judging the absence of an error or deciding a line control signal at the time of judging its presence. CONSTITUTION:Signals obtained by adding respectively different error detection signals A, B to a sound signal and a line control signal whose generation probability is lower than that of the sound signal and coding respective signal-added signals are received by a terminal 31 through a line. A coded signal 104 extracted from the received signals through a demodulator 41 and a packet decomposing circuit 42 is temporarily stored in a buffer 44 and then a receiving signal judging circuit 43 judges the existence/ absence of an error by means of the signal A. There is no error, the circuit 43 decides the signal as a sound signal and a sound decoding circuit 45 decodes the signal 104 and outputs a sound. At the time of detecting an error, the signal is judged as a control signal and a control signal error detecting circuit 46 outputs only a correct control signal based upon the signal B. Consequently highly efficient multiplex signal transmission can be attained without adding an ID signal to a transmitting signal.

公开(公告)号：JPH04364621A

公开(公告)日：1992-12-17

申请号：JP13934991

申请日：1991-06-12

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO ,  TANAKA SHUICHI

IPC: H04L1/22 ,  H04L7/08

Abstract: PURPOSE:To switch a line while the quality of a transmission signal is kept by starting the transmission of a standby line when the quality of the transmission signal of an active line is degraded and switching the line when synchronization is taken. CONSTITUTION:When a bit error rate reaches a prescribed rate or above, as soon as a line switching signal is sent to a line switching device 10 and a frame synchronization detector 9, the signal transmission in a standby line is started. Then the detector 9 implements frame synchronization based on a transmission signal sent through the standby line and after the frame synchronization in the standby line is confirmed, the switching device 10 is used to switch the line. Since the active line and the standby line are switched between a transmission frame and a frequency, the active and standby lines are switched without causing error correction disabling state of the signal caused when the switching is implemented in the frame of the transmission signal.

公开(公告)号：JPH04132346A

公开(公告)日：1992-05-06

申请号：JP25310590

申请日：1990-09-21

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI ,  NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H04L27/34 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE:To attain accurate error correction by storing a signal pattern of a frame synchronizing signal sent from a sender side equipment changed by a phase rotation of a recovered carrier as a comparison pattern in advance and comparing the signal pattern of a demodulated frame synchronizing signal with the comparison pattern. CONSTITUTION:A frame synchronizing signal having preset signal patterns x2, x3, y2, y3 in response to signal point arrangement of the rotation symmetry arrangement differential conversion system is sent from a sender side radio equipment A and change patterns x2, x3, y2, y3 of a transmission frame synchronizing signal by the phase uncertainty of the recovered carrier are stored in a frame synchronizing circuit 72 of a radio equipment B of a receiver side as comparison patterns. Then the signal pattern of the demodulated frame synchronizing signal is compared with the comparison pattern to establish frame synchronization. Thus, an error correction circuit and demodulator 73 applies accurate error correction to the correct frame synchronization.

公开(公告)号：JPH02155314A

公开(公告)日：1990-06-14

申请号：JP30873388

申请日：1988-12-08

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: G06F11/10 ,  G06F7/552 ,  H03M13/00

Abstract: PURPOSE:To attain miniaturization of a circuit and systolic array formation and to simplify the control by repeating (m-1) times the operation of multiplying an element (x) by a finite element (x) and squaring the product, and calculating an inverse element x . CONSTITUTION:The element is inputted in 4-bit parallel from an input terminal 101 and fed to a square circuit 102. An input inputted from the input terminal 101 and an output x from the square circuit 102 are fed to an (M-0) multiplier 103, from which a product x is obtained and fed to a square circuit 104. The element (x) retarded by a delay circuit 105 and an output x of the square circuit 104 are fed to an M-0 multiplier 106, from which a product x is obtained and fed to a square circuit 107. A value x =x obtained from the square circuit 107 is outputted in 4-bit parallel from an output terminal 108. In general, the inverse element circuit of a GF(2 ) in normal base expression consists of (m-2) sets of (M-0) multipliers and (m-1) sets of square circuits.

公开(公告)号：JPH0230240A

公开(公告)日：1990-01-31

申请号：JP17893388

申请日：1988-07-20

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: H03M13/00 ,  H04L1/00

Abstract: PURPOSE:To employ a single equalizer so as to attain coding of plural error correction codes requiring different error correction capability by adding a prescribed invalid information bit equivalent to deficiency to short bit information and supplying the information having a prescribed bit length through the provision of the invalid information bit to a coding means. CONSTITUTION:A control circuit 3 divides the bit length of information desired to be sent from an information source 1 depending on the degree of instability when a communication line 9 is unstable or the importance of the information is high. Thus, a short bit stored in a memory 5 is coded into an error correction code by a coder 7. An invalid information bit equivalent to a short and deficient bit length is added to the short bit information, the resulting information is converted into a usual prescribed bit length and fed to the coder 7. The syndrome is fed to a decoder 23, where an error pattern is obtained. The error pattern is fed to an error correction execution circuit 27 together with a received word passing through a delay circuit 29 and fed to a receiver 31 after the error is corrected.

公开(公告)号：JPH01300732A

公开(公告)日：1989-12-05

申请号：JP13038488

申请日：1988-05-30

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO

IPC: H04L1/18

Abstract: PURPOSE:To improve the probability of proper reception by reducing the probability of the occurrence of error in reproduced blocks at every retransmission by storing and synthesizing likelihood whenever the retransmission is repeated and, even when the quality of the transmission line is extremely inferior, repeating the retransmission CONSTITUTION:A redundancy bit for error control is added to transmitting information sent one block by one block so that the receiving side can discriminate whether or not an error is included in received signals. When the receiving side returns 26 a retransmission requesting signal to the transmitting side upon detecting the error, the information accumulated in an information storing means 32 on the transmitting side is retransmitted by means of an information reproducing means. On the receiving side, the likelihood is calculated and stored in a likelihood accumulating means 29 at every bit or symbol of received signals so that the first received information can be utilized for discriminating the reception of retransmitted signals even when the first transmission is unsuccessful. In other words, bits or symbols are reproduced from the likelihood obtained by synthesizing the likelihood at every bit or symbol of retransmitted signals and the likelihood of the stored first transmitted signals.

公开(公告)号：JPH01289322A

公开(公告)日：1989-11-21

申请号：JP11830288

申请日：1988-05-17

Applicant: TOSHIBA CORP

Inventor： KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: H03M13/00

Abstract: PURPOSE:To decrease number of stored error patterns, to make the memory capacity small and to reduce the processing time by providing a means using a generation polynomial as to a syndrome obtained through the calculation of a reception code as a modulus, multiplying the result by (x) and obtaining a code series and storing only one of error patterns made equal to each other while being shifted sequentially. CONSTITUTION:A syndrome calculation circuit 2 uses a generation polynomial G(X) to calculate a syndrome S(X) from a received code R(X) and multiplies the obtained syndrome S(X) by a factor of (x) by taking the generation polynomial G(X) as a modulus. A specific error pattern is stored by a conversion table 6 and a shift circuit 8 and an error pattern corresponding to a syndrome or a series being a multiple of (x) of it is detected. A means replacing the detected error pattern cyclicly and a means 9 executing error correction are provided. As to each error pattern made equal while being shifted sequentially in this way, only one of them is stored. Thus, the capacity of conversion table is decreased considerably and the processing time is reduced.

公开(公告)号：JPH01238230A

公开(公告)日：1989-09-22

申请号：JP6356888

申请日：1988-03-18

Applicant: TOSHIBA CORP

Inventor： NAKAMURA MAKOTO ,  KODAMA TOMOKO

IPC: H03M13/00

Abstract: PURPOSE:To improve a correcting capability by providing a symbol error correcting and encoding means of transmitting data and an error detecting check bit adding means in a transmitting side and providing an error detecting means by the use of a check bit and a correcting and decoding means for an error symbol in a receiving side by considering it to be an erasing. CONSTITUTION:Data signals a1-a9 are received to a terminal 10, converted to codes b1-b15 in an error correcting encoder 21, then, the error detecting bits p1-p15 are added in the error detecting and encoder 22 and transmitted. A signal including the error generated on a transmission path is received in a detecting circuit 32, the detecting check bits p1-p15 are removed and fed to an erased error correcting decoder 33 and the position information of the error detected code is fed to the decoder 33. The decoder 33 corrects the error clear in an error (X) position as well as an error unclear in the position, correctly recovers original information a1-a9 and outputs to a terminal 13. According to this constitution, the high correcting capability can be obtained with few redundant symbols.