BURST SYNCHRONIZING SYSTEM FOR TIME DIVISION MULTIPLE ACCESS SATELLITE COMMUNICATION SYSTEM

    公开(公告)号:JPS6484927A

    公开(公告)日:1989-03-30

    申请号:JP24138187

    申请日:1987-09-26

    Abstract: PURPOSE:To exactly control a transmission timing of a data burst by a simple circuit even if a slave station is a fixed station or a mobile station by providing a table in which a signal arrival time difference to a moving position of the slave station is stored in advance. CONSTITUTION:Each slave station is provided with a table 100 in which a difference between a signal arrival time extending from the own station to a communication satellite and a signal arrival time extending from a reference station to the communication satellite is stored in advance at every position of the own station, and also, provided with a sending-out timing control means 200 for controlling a sending-out timing of a data burst in accordance with output information of this table 100. In this state, in each slave station, by inputting a position of the own station to this table 100, a signal arrival time difference corresponding to this position is outputted, and in accordance with the signal arrival time difference outputted from the table 100, the sending-out timing of the data burst based on the receiving timing of a reference burst as a reference is controlled by the means 200. As a result, by only inputting a position of each time of the slave station, an optimum transmission timing corresponding to its position can always be set.

    SATELLITE COMMUNICATION SYSTEM
    2.
    发明专利

    公开(公告)号:JPS6447136A

    公开(公告)日:1989-02-21

    申请号:JP20340287

    申请日:1987-08-18

    Applicant: TOSHIBA CORP

    Abstract: PURPOSE:To reduce the processing time by inserting a processing request representing plural processing processes to one control signal from plural earth stations or centralized control stations and sending the result and executing the request by an opposite earth station or the like according to the processing process set in response to the kind of communication processing in advance. CONSTITUTION:A processing request sending means 100 provided to an earth station or a centralized control station generates information representing plural processing requests required for the reset processing or the like and inserts it to one control signal and sends the result to the opposite earth station via a common signal line. The opposite earth station discriminates the kind of the signal from the processing request inserted in the signal and executes the plural processing processes corresponding to the kinds of the signal preset in a communication processing execution means 200. Thus, the number of times of transmitting the control signal required for one communication processing is reduced and the required time of the communication processing in the earth station is reduced.

    LEVEL CONTROL CIRCUIT
    3.
    发明专利

    公开(公告)号:JPH02162850A

    公开(公告)日:1990-06-22

    申请号:JP31711988

    申请日:1988-12-15

    Applicant: TOSHIBA CORP

    Abstract: PURPOSE:To eliminate waveform distortion of a burst signal output after data correction by correcting the level of a reception burst signal information in accordance with the reception data of a burst signal for each time slot. CONSTITUTION:A reception burst signal Bi is delayed by a delay circuit 11, amplified by an amplifier 12 and inputted to an attenuator 13. On the other hand, a detector 14 detects the reception burst signal Bi and a ROM 16 outputs a level correction data Dli stored in an address corresponding to an output signal Bidd of an A/D converter 15 and stores in a register 17 tentatively. Then the attenuator 13 controls the attenuation quantity in response to the level correction quantity signal LCi from the D/A converter 19 and the reception burst signal Bi is corrected and output to a prescribed level for each time slot. Thus, no waveform distortion exists in an output burst signal Bio after level correction and a demodulation signal without any demodulation distortion is obtained.

    UNIQUE WORD DETECTION CIRCUIT
    4.
    发明专利

    公开(公告)号:JPH0378338A

    公开(公告)日:1991-04-03

    申请号:JP21558989

    申请日:1989-08-22

    Applicant: TOSHIBA CORP

    Inventor: SAHO AKEMI

    Abstract: PURPOSE:To stably detect a unique word without adjustment by calculating the number of optimum allowable error bits with which the non-detection rate of the unique word and the erroneous detection rate become minimum at the condition of an estimated code error rate and setting the above number to the unique word detection circuit main body. CONSTITUTION:A reception burst signal RD is decoded in a decoding circuit 20 and is guided to a unique word detection circuit mainbody 11. At that time, a pass matrix obtained in a decoding process in the decoding circuit 20 is guided to a code error estimation circuit 12. The code error rate estimation circuit 12 obtains the time mean value of the pass matrix and the code error rate CS at that time is obtained from the time mean value. Then, the code error rate CS is supplied to ROM 13 as an address. Thus, the number of the optimum allowable error bits HS corresponding to the code error rate CS is read from a storage area corresponding to the address in the ROM 13 and the number of the optimum allowable error bits HS is supplied and set to the unique word detection circuit mainbody 11. Thus, the unique word is detected stably without adjustment.

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