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公开(公告)号：JP2001203470A
公开(公告)日：2001-07-27
申请号：JP2000012795
申请日：2000-01-21
Applicant: TOSHIBA CORP
Inventor： ARIMA SHUICHI , SHIMADA OSAMU
Abstract: PROBLEM TO BE SOLVED: To prevent generation of crosstalks and increase in size to the utmost, when signal wirings are arranged with high density. SOLUTION: In a wiring board having a plurality of wiring layers, a plurality of terminals 4a, 4b, 6a, 6b for signal wiring and a plurality of terminals 3, 5, 7 for power source are arranged on the main surface of the wiring board. The terminals for signal wiring or the terminals for power source are connected with any one of inner layers of the wiring layers. Among the plurality of terminals for signal wiring, the terminals 4a, 4b connected with the wiring formed on the same layer are arranged so that at least one among the inner side and the outer side of a region where the terminals 4a, 4b are formed is surrounded by the terminals 3, 5 for power source.
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公开(公告)号：JPH0964226A
公开(公告)日：1997-03-07
申请号：JP21373395
申请日：1995-08-22
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU , FUKUOKA YOSHITAKA
Abstract: PROBLEM TO BE SOLVED: To perform the reductions of the cost and size of a semiconductor package, etc., by mounting in a burying way a semiconductor chip in the mounting cavity of a wiring board to seal with a resin the mounting region thereof in the form of no sealing resin exceeding the surface of the wiring board. SOLUTION: A semiconductor package has at least one semiconductor-chip mounting cavity 11 with both its step-tape sidewall surfaces, an alumina based wiring board 10 with disposed connection terminals 12 in the step portions of the cavity 11, a semiconductor chip 13 mounted in a burying way in the cavity 11, and bonding wires 14 for connecting the input/output pads of the semiconductor chip 13 with the corresponding connection terminals 12 thereto. Further, the semiconductor package comprises a resin sealing layer 15 for enclosing both the semiconductor chip 13 and the bonding wires 14 in the cavity 11 without exceeding the surface of the wiring board 10 with the formed cavity 11, and I/O leads 16 drawn out on the surface side of the resin-sealed wiring board 10. Thereby, since the resin-sealed surface of the mounted chip parts is not protruded from the surface of the wiring board 10, the flatness and thickness of the semiconductor package are secured easily.
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公开(公告)号：JPH098442A
公开(公告)日：1997-01-10
申请号：JP15744295
申请日：1995-06-23
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU , MOTOMURA TOMOHISA , FUKUOKA YOSHITAKA
Abstract: PURPOSE: To provide a wiring board for mounting use formed into a structure, wherein the reliability of the connection of bump electrodes with the input/output terminals of a semiconductor element, which is caused by an irregularity in the heights of the electrodes, can be improved, and to bring out the high-reliability function of the wiring board while the cost of the wiring board is prevented from being increased. CONSTITUTION: A wiring board for mounting use is formed into a structure, wherein the wiring board has a wiring board main body 4 for mounting use and bump electrodes 4a for connection use provided on the surface of the main body 4 and the point surfaces of the electrodes 4a are formed into a multilayer structure consisting of a high-hardness conductor layer 4a,. In more concrete terms, the wiring board is formed into a structure, wherein the bump electrodes 4a, which are connected with input/output terminals of a semiconductor element, are provided on the surface of the main body 4, the sides, which face the surfaces of conductor pads 4b1 of the electrodes 4a are formed into a multilayer structure consisting of a comparatively low-hardness conductor layer 4a1 and the point surfaces of the electrodes 4a are formed into the multilayer structure consisting of the high-hardness conductor layer 4a2 .
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公开(公告)号：JPH08125099A
公开(公告)日：1996-05-17
申请号：JP26525494
申请日：1994-10-28
Applicant: TOSHIBA CORP
Inventor： YAMAZAKI TAKASHI , OOSHIMA YUMIKO , HIRAI HIROYUKI , ONO JUNICHI , FUKUOKA YOSHITAKA , SHIMADA OSAMU
Abstract: PURPOSE: To prevent the unevenness of the wettability of a brazing material and to improve the wettability of the material by forming the atmosphere at the time of brazing and heating to mixed atmosphere of hydrogen - nitrogen including hydrogen gas with a specific numeric value range at a brazing process of an input/output(I/O) lead terminal. CONSTITUTION: A brazing material pellet 6 is mounted on the surface of the contact pad 5 of a ceramic package type semiconductor device body. The I/O lead terminal 7 of a lead frame is aligned with the surface of the pellet 6, disposed, and the connecting part of the terminal 7 is pressed by a brazing jig 10. It is set in a tunnel type sealing furnace in this state, the pellet is melted by conveying and heating, and the surface of the pad 5 is brazed and connected to the connecting part of the terminal 7. The atmosphere at the time of brazing and heating is set to the mixed atmosphere of hydrogen and nitrogen containing 60 to 90vol.% of hydrogen gas, thereby suppressing the unevenness of the wettability of the material, and further improving the wettability of the material.
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公开(公告)号：JPH07154041A
公开(公告)日：1995-06-16
申请号：JP27288293
申请日：1993-11-01
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU
Abstract: PURPOSE:To obtain a wiring board in which the signal propagation delay time is shortened while suppressing skew by branching the signal wiring sequentially from a reference point to a plurality of input terminals in the order of linear distance between the reference point and the input terminal. CONSTITUTION:Signal lines are branched sequentially from a reference point 5 to a plurality of input terminals 9 in the order of the linear distance therebetween. For example, an output pad 3 of a first semiconductor device 2 mounted on a wiring board 1 is connected by a bonding wire 4 to an output terminal 5 on the wiring board 1. The wiring 6 from the output terminal 5 is branched, in the order of the linear distance from the output terminal 5, to the input terminals 9a-9f on the wiring board 1 connected by the bonding wire 4 with the input pads 8a-8f on a second semiconductor device 7. Wiring length adjusting parts 10a-10e are inserted, with reference to the output terminal 5, in order to match the operating timing at the input terminals 9a-9f.
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Patent Agency Ranking
公开(公告)号：JPH06265599A
公开(公告)日：1994-09-22
申请号：JP5427593
申请日：1993-03-15
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU
Abstract: PURPOSE:To provide a multichip module in which the internal wiring can be set at a desired potential and burn-in test can be carried out positively under module state. CONSTITUTION:A second power supply wiring 5 and a second ground wiring 2 are provided in addition to first power supply wiring 1 and first ground wiring 6. An internal wiring 4 connecting between semiconductor chips IC1 and IC2 is connected through a resistor R1 with the second power supply wiring 5 and through a resistor R2 with the first ground wiring 6. The second power supply wiring 5 and the first ground wiring 6 are not connected directly with the semiconductor chips IC1, IC2, etc., but connected with outer terminals 15, 16.
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公开(公告)号：JPH0637450A
公开(公告)日：1994-02-10
申请号：JP19079392
申请日：1992-07-17
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU
Abstract: PURPOSE:To provide a multilayered thin-film printed-circuit board capable of reliable connection by forming I/O terminals, each having a non-buffering composite structure of different metal layers and being isolated electrically from the substrate surface. CONSTITUTION:A first interconnection layer 2a, and underlays 3a for I/O terminals 3 are provided on the surface of an insulating substrate 1. The layers 2a and 3a each include a refractory metal layer and an aluminum layer. The entire surface of the substrate, except part of the surface of the individual underlays, is covered with an insulating layer 2d. A protective layer is formed around the inner insulating layer 2d and the underlays 3a, and interconnection layers 2b and 2c and another inner insulating layer 2d are formed to provide a multilayered thin-film interconnection 2. The interconnection layers 2b and 2c are extended to connect the underlay 3a, and a contact layer 3c for an I/O terminal 3 is provided. The uppermost interconnection layer 2c is then covered with a protective insulating layer 2d'. In this manner a reliable, multilayered thin-film printed circuit board is obtained.
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公开(公告)号：JPH04371588A
公开(公告)日：1992-12-24
申请号：JP14838991
申请日：1991-06-20
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU
Abstract: PURPOSE:To provide a device of simple structure capable of easily and surely detecting the etching end point of a work with simple operation. CONSTITUTION:This detector is provided with a light source 13 from which a work 1 to be etched is irradiated with ionizing radiation or light and a light- receiving part 14 for detecting the transmitted light quantity or reflected light quantity of the ionizing radiation or light with which the work 1 is irradiated. Since the reflection of light is changed as the etching of the work 1 such as a metal layer formed on the surface of a support 1a proceeds, the etching end point is detected utilizing the transmission or reflection of light.
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公开(公告)号：JPH03170916A
公开(公告)日：1991-07-24
申请号：JP31211489
申请日：1989-11-29
Applicant: TOSHIBA CORP
Inventor： OGAWA MEIKO , IKEDA MITSUSHI , SHIMADA OSAMU
IPC: G02F1/1333 , G02F1/1343 , G02F1/1345 , G09F9/30
Abstract: PURPOSE:To avoid the deterioration of the picture quality in long-time operation and to improve the quality by surrounding a pattern formed in the display region by a first signal wiring layer with a seal part and making the pattern continuous once by a material constituting a second signal wiring layer in the region between the seal part and the display region. CONSTITUTION:The first signal wiring layer 2 in the display region in the liq. crystal driving semiconductor device substrate is cut outside the display region 6 and in the region surrounded by the seal part 5, brought into contact with the material constituting the second signal wiring layer 4 at least once through a through hole 7 bored in the interlayer insulating layer 3 and led outside the region surrounded by the seal part 5. Accordingly, the diffusion of the minute crack generated in the first signal wiring layer 2 in the thermal or sealing stages where a high pressure is locally applied in the producing or assembling process to the display region 6 is effectively prevented or avoided. Consequently, the picture quality is not deteriorated in long-time operation, and the necessary display function is maintained and exhibited at all times.
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公开(公告)号：JPH03116116A
公开(公告)日：1991-05-17
申请号：JP25488189
申请日：1989-09-29
Applicant: TOSHIBA CORP
Inventor： SHIMADA OSAMU
IPC: G02F1/1335 , G02F1/1343
Abstract: PURPOSE:To increase light transmittance and to enable satisfactory washing before assembling by forming color filter layers arranged on one of first and second substrates holding a sealed liq. crystal layer between them with electrically conductive transparent films separately contg. colorants. CONSTITUTION:A black matrix pattern 2 of a thin Cr film is formed on a substrate 1 and red, green and blue color filter layers 3-5 are arranged on the substrate 1 with the pattern 2 in stripes with a prescribed cycle. The color filter layers 3-5 are electrically conductive transparent films separately contg. red, green and blue pigments and act as a transparent electrode confronting a display electrode on an active matrix substrate. Since a gelatin layer and a resin layer for flattening the surface of the gelatin layer are made unnecessary, light transmittance is increased and washing before assembling can easily be carried out.
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