公开(公告)号：JP2012108369A

公开(公告)日：2012-06-07

申请号：JP2010258009

申请日：2010-11-18

Applicant: TOSHIBA CORP

Inventor： NAKAMURA HIROKO ,  ASAKAWA KOUJI ,  HATTORI SHIGEKI ,  TANAKA SATOSHI ,  KOTANI TOSHIYA

IPC: G03F7/039 ,  C08F297/00 ,  G03F7/004 ,  G03F7/038 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a pattern formation method whereby a periodic pattern and a non-periodic pattern can be formed at a low cost by using the self organization of a block copolymer.SOLUTION: In the pattern formation method according to the present embodiment, a pattern including first block phases and second block phases is formed by causing the self-organization of block copolymer on a processed film. The entire block copolymer present in a first area is removed by carrying out exposure and development under a first condition, and patterns including the first block phases and the second block phases are left in areas other than the first area. In addition, the first block phases present in the second area are selectively removed by carrying out exposure and development under a second condition, and patterns including the first block phases and second block phases are left in the areas where the areas other than the first area and the areas other than the second area overlap. In addition, a pattern with the second block phases is left in the second area except the overlapping area, and the processed film is etched using the remaining pattern as a mask.

公开(公告)号：JP2011215627A

公开(公告)日：2011-10-27

申请号：JP2011127221

申请日：2011-06-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TAKAHASHI MASANORI ,  KOTANI TOSHIYA ,  TANAKA SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a method for evaluating a pattern layout for accurately calculating a pattern formation defect region caused by a step pattern, in a short time.SOLUTION: The method for evaluating a pattern layout comprises: calculating a pattern formation defect region by using a correspondence relation between a distance from a pattern formed through a lithographic process in a formed film covering a step portion to the step portion, and the possibility that the formed pattern becomes a pattern formation defect region, and by using the layout of the step portion; and extracting a pattern formation defect region by comparing the calculated pattern formation defect region and the layout of the formed pattern. The correspondence relation is a function representing the correspondence relation, and is prepared based on the exposure conditions or process conditions for forming the step portion. The pattern formation defect region is calculated by performing convolution operation of the correspondence relation on the layout used for forming the step portion.

Abstract translation: 要解决的问题：提供一种用于评估在短时间内精确地计算由步进图形引起的图案形成缺陷区域的图案布局的方法。解决方案：用于评估图案布局的方法包括：计算图案形成缺陷区域 通过使用从形成在通过平版印刷工艺形成的图案的距离到覆盖台阶部分的成形薄膜的距离与形成图案变成图案形成缺陷区域的可能性之间的对应关系，并且通过使用 步骤部分 以及通过比较所计算的图案形成缺陷区域和形成的图案的布局来提取图案形成缺陷区域。 对应关系是表示对应关系的函数，并且基于用于形成台阶部分的曝光条件或处理条件来准备。 通过对用于形成台阶部的布局进行对应关系的卷积运算来计算图形形成缺陷区域。

公开(公告)号：JP2010276960A

公开(公告)日：2010-12-09

申请号：JP2009130892

申请日：2009-05-29

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SANHONGI AKIKO ,  TANAKA SATOSHI ,  TAKAHASHI MASANORI ,  TAKEKAWA YOKO ,  TAKAGI TAKAMASA ,  KODERA KATSUMASA ,  KAWAGUCHI HIDEKAZU

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70

CPC classification number: G03F1/26

Abstract: PROBLEM TO BE SOLVED: To provide a method of making a phase shift mask or mask data of the phase shift mask, for reducing focus deviation due to the structure of a photomask for a plurality of mask patterns; and to provide a method of manufacturing a semiconductor device. SOLUTION: The phase shift mask, which includes transmission parts for transmitting exposure light and light-shielding parts for intercepting at least a portion of the exposure light, and has a plurality of mask patterns with at least one of pitch and pattern dimension differentiated from one another, or the mask data of the phase shift mask is prepared. An exposure experiment or an exposure simulation is performed by using the phase shift mask in which engraving is formed in an area constituting the transmission part, or the mask data, superposition of respective focus ranges when the exposure result satisfies desired dimensions is obtained, the depth of the engraving when the superposition of the determined focus ranges satisfies permissible condition is obtained, and the phase shift mask provided with the engraving having the engraving depth or the mask data of the phase shift mask is making. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造相移掩模的相移掩模或掩模数据的方法，用于减少由于多个掩模图案的光掩模的结构引起的聚焦偏差; 并提供一种制造半导体器件的方法。 解决方案：相移掩模，其包括用于透射曝光光的透射部分和用于截取曝光光的至少一部分的遮光部分，并且具有多个具有节距和图案尺寸中的至少一个的掩模图案 彼此区分，或准备相移掩模的掩模数据。 曝光实验或曝光模拟是通过使用在构成透射部分的区域中形成雕刻的相移掩模，或者当获得曝光结果满足期望尺寸时掩模数据，各个焦点范围的叠加，深度 当确定的焦距范围的叠加满足允许条件时，获得雕刻的相位移动掩模，并且提供具有相移掩模的雕刻深度或掩模数据的雕刻的相移掩模。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010156866A

公开(公告)日：2010-07-15

申请号：JP2008335484

申请日：2008-12-27

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SATAKE MASAKI ,  ASANO MASASHI ,  TANAKA SATOSHI ,  UNO TAIGA

IPC: G03F1/68 ,  G03F1/70 ,  G06F17/50

CPC classification number: G03F1/44 ,  G03F7/705

Abstract: PROBLEM TO BE SOLVED: To provide a feature-quantity extracting method in which feature quantities can be extracted, before a resist model is optimized and to provide a test pattern selecting method, a resist model creating method and a designed-circuit-pattern verifying method. SOLUTION: The feature-quantity extracting method, in which feature quantities are extracted from optical images of a pattern of a photomask, by using feature-quantity extraction functions for calculating feature quantities to be used as explanatory variables of the resist model for predicting a resist image, includes: a step of setting feature-quantity extraction parameters (steps S13 and S14); and a step of causing the feature-quantity extraction functions, the feature-quantity extraction parameters of which are set at the steps of setting feature-quantity extraction parameters, to make it act on optical images and calculating feature quantities from the optical images (step S15). COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供在抗蚀剂模型被优化之前可以提取特征量的特征量提取方法，并且提供测试图案选择方法，抗蚀剂模型创建方法和设计电路 - 模式验证方法。 解决方案：通过使用用于计算要用作抗蚀剂模型的解释变量的特征量的特征量提取函数，从特征量提取函数中提取特征量，其特征量是从光掩模图案的光学图像中提取的， 预测抗蚀图像包括：设置特征量提取参数的步骤（步骤S13和S14）; 以及在特征量提取参数的步骤中设置的特征量提取参数使其作用于光学图像并从光学图像计算特征量的步骤（步骤 S15）。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009210635A

公开(公告)日：2009-09-17

申请号：JP2008050804

申请日：2008-02-29

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SATOSHI ,  SATAKE MASAKI

IPC: G03F1/68 ,  G03F1/70 ,  H01L21/027

CPC classification number: G03F1/36 ,  G03F1/80

Abstract: PROBLEM TO BE SOLVED: To provide a pattern prediction method and a pattern correction method allowing prediction or correction of a high accuracy feature without increasing a process time, and to provide a method for manufacturing a semiconductor device, and a program. SOLUTION: The pattern prediction method includes predicting a feature of a second pattern from a feature of a first pattern by using the following functions: a conversion function that correlates a first pattern formed in a first step and a second pattern formed in a second step subsequent to the first step, on the basis of the contours of the first and the second patterns; and a conversion difference residue function that correlates a residual amount between a predicted feature of the second pattern obtained by the conversion function and a feature of the second pattern actually obtained by applying the second step, to factors except for the contours of the first and the second patterns. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许在不增加处理时间的情况下预测或校正高精度特征的图案预测方法和图案校正方法，以及提供半导体器件的制造方法和程序。 解决方案：图案预测方法包括通过使用以下功能从第一图案的特征预测第二图案的特征：将在第一步骤中形成的第一图案和形成在第一图案中的第二图案相关联的转换功能 基于第一和第二图案的轮廓的第一步之后的第二步骤; 以及转换差分残差函数，其将通过转换函数获得的第二图案的预测特征与通过应用第二步骤实际获得的第二图案的特征之间的剩余量相关联，除了第一和第二图形的轮廓之外的因素 第二种模式。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009170776A

公开(公告)日：2009-07-30

申请号：JP2008009218

申请日：2008-01-18

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ENDO AYAKO ,  KOTANI TOSHIYA ,  YOSHIDA KENJI ,  TANAKA SATOSHI

IPC: H01L21/02 ,  H01L21/027

CPC classification number: G05B19/41865 ,  G05B19/41885 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/20 ,  Y02P90/26 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To improve robust properties on productions to performance variations among semiconductor production devices when there are a plurality of the production devices used for producing semiconductor products. SOLUTION: Danger points are extracted in consideration of the performance variations of exposure systems used for the productions having effects on finishing shapes on substrates. When process capabilities at the danger points are lower than desired ones on a production planning, the process capabilities at the danger points are improved by the changes or the like of process conditions. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：当存在用于制造半导体产品的多个生产装置时，为了提高对半导体制造装置中的性能变化的生产力的鲁棒性能。

解决方案：考虑到用于对基板上的精加工形状产生影响的生产的曝光系统的性能变化，提取危险点。 当危险点的过程能力低于生产计划中所需的过程能力时，通过过程条件的变化等改善危险点的过程能力。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008199054A

公开(公告)日：2008-08-28

申请号：JP2008105171

申请日：2008-04-14

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NAKAMURA HIROKO ,  KOTANI TOSHIYA ,  TANAKA SATOSHI ,  SANHONGI SHOJI

IPC: G03F1/92 ,  H01L21/027 ,  G03C5/00 ,  G03F7/40 ,  G03F9/00 ,  G06F17/50 ,  H01L21/28 ,  H01L21/768

CPC classification number: G03F7/0035 ,  G03F1/92 ,  G03F7/40

Abstract: PROBLEM TO BE SOLVED: To improve processing dimension accuracy for a film to be processed in a technology which superimposes a plurality of resist films to form a mask and processes the film to be processed.
SOLUTION: Step ST11: Design pattern data are prepared in which contact holes are arranged on a part of grid points in matrix. Step ST12: First mask pattern data are prepared in which first opening patterns are arranged on all of the grid points. Step ST13 - Step ST15: Second mask pattern data are designed in which second opening patterns and third opening patterns are overlapped, wherein the second opening patterns are arranged on the grid points, at which the contact holes are arranged, in the design pattern data to include the first opening patterns, and the third opening patterns are arranged on a pair of the grid points, which are a pair of diagonal grid points of four grids composing a unit grid, only on which the contact holes are arranged.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提高叠加多个抗蚀剂膜以形成掩模并处理待处理的薄膜的技术，提高待处理薄膜的加工尺寸精度。 解决方案：步骤ST11：制备设计图案数据，其中接触孔布置在矩阵中的网格点的一部分上。 步骤ST12：准备第一掩模图案数据，其中在所有网格点上布置有第一开口图案。 步骤ST13-步骤ST15：设计第二开口图案和第三开口图案重叠的第二掩模图案数据，其中第二开口图案布置在布置有接触孔的网格点上，在设计图案数据中 包括第一开口图案，并且第三开口图案布置在一对网格点上，该对网格点是构成单位格栅的四个格栅的一对对角网格点，仅在其上布置有接触孔。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008122929A

公开(公告)日：2008-05-29

申请号：JP2007245064

申请日：2007-09-21

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ASANO MASASHI ,  SATAKE MASAKI ,  TANAKA SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  H01L21/3065

CPC classification number: G03F7/70425 ,  G03F7/70491 ,  G03F7/705 ,  G03F7/70616

Abstract: PROBLEM TO BE SOLVED: To provide a method for creating a simulation model capable of performing high accuracy simulation. SOLUTION: The method includes: a step S11 of defining feature factors featuring the pattern layout of a mask pattern; a step S12 of defining control factors that influence the dimension of a resist pattern to be formed on a substrate through lithographic processes using the mask pattern; a step S13 of obtaining a predicted dimension of a resist pattern to be formed on the substrate by lithographic processes using the mask pattern by using a model based on the feature factors and the control factors; a step S14 of acquiring the actual dimension of a resist pattern actually formed on the substrate through lithographic processes using the mask pattern; and a step S15 of structuring a neural network by setting the feature factors, the control factors and the predicted dimension to an input layer and setting the actual dimension to an output layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于创建能够执行高精度模拟的仿真模型的方法。 解决方案：该方法包括：定义以掩模图案的图案布局为特征的特征因子的步骤S11; 通过使用掩模图案的光刻处理来限定影响要在基板上形成的抗蚀剂图案的尺寸的控制因素的步骤S12; 步骤S13，通过使用基于特征因子和控制因子的模型，通过使用掩模图案的光刻处理来获得要在基板上形成的抗蚀剂图案的预测尺寸; 通过使用掩模图案的光刻处理来获取实际形成在基板上的抗蚀剂图案的实际尺寸的步骤S14; 以及通过将特征因子，控制因子和预测尺寸设置到输入层并将实际尺寸设置为输出层来构造神经网络的步骤S15。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008122718A

公开(公告)日：2008-05-29

申请号：JP2006307258

申请日：2006-11-13

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NAGAI SATOSHI ,  FUKUHARA KAZUYA ,  ITO MASAMITSU ,  KAWANO KENJI ,  TANAKA SATOSHI

IPC: G03F1/62 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/62 ,  G03F7/70158 ,  G03F7/70191

Abstract: PROBLEM TO BE SOLVED: To provide a photomask unit having an optimized pellicle. SOLUTION: The photomask unit 10 comprises a mask substrate 20 having a pattern arranged with a pitch P and a pellicle 30 protecting the mask substrate. The pellicle is configured to maximize the transmittance for incident light at an incident angle θ defined by sinθ=λ/(2P), wherein λ represents the wavelength of the incident light. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有优化防护薄膜的光掩模单元。 解决方案：光掩模单元10包括具有以节距P布置的图案的掩模基板20和保护掩模基板的防护薄膜30。 防护薄膜组件被配置为使入射光的透射率以由sinθ=λ/（2P）定义的入射角θ最大化，其中λ表示入射光的波长。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007286362A

公开(公告)日：2007-11-01

申请号：JP2006113692

申请日：2006-04-17

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SATAKE MASAKI ,  TANAKA SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  H01L21/027

CPC classification number: G03F7/70666 ,  G03F7/705

Abstract: PROBLEM TO BE SOLVED: To provide a simulation method for performing high accuracy lithography simulation by an easy method.
SOLUTION: The method includes: a step S2 of obtaining a mask transmission function from a mask layout; a step S3 of obtaining an optical image of the mask layout by using the mask transmission function; a step S4 of applying a predetermined function filter to the mask transmission function to obtain a filtered function; and a step S5 of correcting the optical image by using the filtered function.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过简单的方法进行高精度光刻模拟的模拟方法。 解决方案：该方法包括：从掩模布局获得掩模传输功能的步骤S2; 通过使用掩模发送功能获得掩模布局的光学图像的步骤S3; 将预定功能滤波器应用于掩模传输功能以获得滤波功能的步骤S4; 以及通过使用滤波函数校正光学图像的步骤S5。 版权所有（C）2008，JPO＆INPIT