Abstract:
An apparatus for the detection of a wearer includes a first inner layer that is adapted to reflect a portion of radar energy back toward its source. A second outer layer is disposed over the first inner layer and it provides a texture and visual appearance that is preferred. For some applications, an especially easy to spot brightly colored visual appearance is preferred for the second outer layer. For other applications, a more subdued visual appearance is preferred. For still other applications, a camouflage appearance is preferred. A space is provided intermediate the first inner layer and the second outer layer accordingly to a modification and an additional material is used to fill the space. The additional material must be substantially transparent to radar energy and it may provide additional floatation capability or additional insulating capability or both to the garment, as desired.
Abstract:
An apparatus for the detection of a person afloat in the water includes a garment portion that is worn by the person. The garment portion preferably includes an inflatable vest. An actuation mechanism detects immersion in the water, preferably at a predetermined depth, and then automatically inflates the vest by puncturing or opening a first container and releasing a gas therein. A balloon is also attached to the vest and is also inflated by the gas of the first container providing the gas in the first container is a lighter-than-air type of a gas that is able to cause the balloon to rise in the air. A tether secures the balloon to the vest. If the gas in the first container is not suitable for filling the balloon, a second container is used that contains the desired lighter-than-air gas and it is also either punctured or otherwise opened by the actuation mechanism so as to inflate the balloon. The balloon automatically releases apart from the vest upon inflation and rises the length of the tether above the person. Devices to manually inflate the vest and the balloon are also described.
Abstract:
The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.
Abstract:
The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.
Abstract:
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.
Abstract:
A process and system is disclosed to assist work planners by assembling a work breakdown structure (WBS) and work flow for a project based on the explicit selection or deselection of outcome(s) by a work planner from a defined set of possible outcomes. The process and system ensure that the resulting project WBS and work flow is composed of the minimum set of activities required to produce the set of outcomes desired for the project. The process and system further ensure that the project's activities are organized into an activity hierarchy defined by a WBS template designated by the work planner, and that each of the project's activities is linked into an appropriate work flow, supported by appropriate instructional or descriptive content.