公开(公告)号：US11791167B2

公开(公告)日：2023-10-17

申请号：US17121546

申请日：2020-12-14

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis ,  Hoyoung Kang

IPC: H01L21/3213 ,  H01L21/321 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/32137 ,  H01L21/32105 ,  H10B43/27 ,  H10B43/35

Abstract: A method of processing a substrate includes forming a channel through a substrate, depositing a layer of polycrystalline silicon on sidewalls of the channel, and oxidizing uncovered surfaces of the polycrystalline silicon with an oxidation agent. The oxidizing agent causes formation of an oxidized layer, the oxidized layer having a uniform thickness on uncovered surfaces of the polycrystalline silicon. The method includes removing the oxidized layer from the channel with a removal agent, and repeating steps of oxidizing uncovered surfaces and removing the oxidized layer until removing a predetermined amount of the layer of polycrystalline silicon.

公开(公告)号：US11776808B2

公开(公告)日：2023-10-03

申请号：US17122898

申请日：2020-12-15

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis ,  Anton deVilliers

IPC: H01L21/02 ,  B05D1/00

CPC classification number: H01L21/02282 ,  H01L21/02134 ,  B05D1/005

Abstract: A method for planarizing a substrate includes: receiving a substrate having microfabricated structures that differ in height across the working surface of the substrate that define a non-planar topography, depositing a first layer that includes a solubility-shifting agent on the working surface of the substrate by spin-on deposition in a non-planar fashion, exposing the first layer to a first pattern of actinic radiation based on the topography, developing the first layer using a predetermined solvent, and depositing a second layer over the working surface of the substrate that has a greater planarity as compared to the first layer prior to developing the first layer. The first pattern of radiation changes a solubility of the first layer such that upper regions of the non-planar topography of the first layer are soluble to the predetermined solvent.

公开(公告)号：US11721551B2

公开(公告)日：2023-08-08

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. Devilliers ,  Daniel J. Fulford ,  Anthony R. Schepis ,  Mark I. Gardner ,  H. Jim Fulford

IPC: H01L21/027 ,  H01L23/16 ,  H01L23/498

CPC classification number: H01L21/0274 ,  H01L23/16 ,  H01L23/49822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US11688642B2

公开(公告)日：2023-06-27

申请号：US17486189

申请日：2021-09-27

Applicant: Tokyo Electron Limited

Inventor： Anton J. Devilliers ,  Daniel J. Fulford ,  Anthony R. Schepis ,  Mark I. Gardner ,  H. Jim Fulford

IPC: H01L21/822 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/8221 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/50

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20220113635A1

公开(公告)日：2022-04-14

申请号：US17463060

申请日：2021-08-31

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis

IPC: G03F7/20 ,  H01L21/027

Abstract: A method of processing a substrate that includes: depositing a photoresist layer over the substrate; performing a cyclic direct-write lithographic process using a direct-write lithography tool, the cyclic direct-write lithographic process including a plurality of cycles, each of the plurality of cycles including: exposing the photoresist layer to a patterned actinic radiation without using a photomask, defining one of a plurality of coupon regions, where the plurality of coupon regions are configured to generate a plurality of test samples on the substrate for evaluating process conditions of a fabrication process; exposing the one of the plurality of coupon regions; and performing the fabrication process on the one of the plurality of coupon regions.

公开(公告)号：US12001147B2

公开(公告)日：2024-06-04

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. Fulford ,  Anthony R. Schepis ,  Mark I. Gardner ,  Anton J. Devilliers ,  H. Jim Fulford

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US11526088B2

公开(公告)日：2022-12-13

申请号：US17404669

申请日：2021-08-17

Applicant: Tokyo Electron Limited

Inventor： Anton J. Devilliers ,  Anthony R. Schepis ,  David Conklin

IPC: G03F7/20 ,  H01L23/544 ,  G06T7/33 ,  G06V10/24 ,  G06T7/00 ,  H01L21/66 ,  G06T7/73 ,  H04N5/225 ,  G03F9/00 ,  G01N21/956

Abstract: Aspects of the present disclosure provide an imaging system. For example, in the imaging system a first light source can generate a first light beam of a first wavelength, a second light source can generate a second light beam of a second wavelength, the second light beam having power sufficient to pass through at least a portion of a thickness of a wafer, an alignment module can coaxially align the second light beam with the first light beam, a coaxial module can focus the coaxially aligned first and second light beams onto a first pattern located on a front side of the wafer and a second pattern located below the first pattern, respectively, and an image capturing module can capture a first image of the first pattern and a second image of the second pattern. The second image can be captured via quantum tunneling imaging or infrared (IR) transmission imaging.

公开(公告)号：US20210305060A1

公开(公告)日：2021-09-30

申请号：US17121546

申请日：2020-12-14

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis ,  Hoyoung Kang

IPC: H01L21/3213 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/321

Abstract: A method of processing a substrate includes forming a channel through a substrate, depositing a layer of polycrystalline silicon on sidewalls of the channel, and oxidizing uncovered surfaces of the polycrystalline silicon with an oxidation agent. The oxidizing agent causes formation of an oxidized layer, the oxidized layer having a uniform thickness on uncovered surfaces of the polycrystalline silicon. The method includes removing the oxidized layer from the channel with a removal agent, and repeating steps of oxidizing uncovered surfaces and removing the oxidized layer until removing a predetermined amount of the layer of polycrystalline silicon.

公开(公告)号：US20210296121A1

公开(公告)日：2021-09-23

申请号：US17122898

申请日：2020-12-15

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis ,  Anton deVilliers

IPC: H01L21/02

Abstract: A method for planarizing a substrate includes: receiving a substrate having microfabricated structures that differ in height across the working surface of the substrate that define a non-planar topography, depositing a first layer that includes a solubility-shifting agent on the working surface of the substrate by spin-on deposition in a non-planar fashion, exposing the first layer to a first pattern of actinic radiation based on the topography, developing the first layer using a predetermined solvent, and depositing a second layer over the working surface of the substrate that has a greater planarity as compared to the first layer prior to developing the first layer. The first pattern of radiation changes a solubility of the first layer such that upper regions of the non-planar topography of the first layer are soluble to the predetermined solvent.