公开(公告)号：US20240170307A1

公开(公告)日：2024-05-23

申请号：US17989333

申请日：2022-11-17

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: H01L21/67 ,  H01L21/687

CPC classification number: H01L21/67103 ,  H01L21/68785

Abstract: According to an embodiment, an apparatus for a hot plate apparatus is disclosed. The hot plate apparatus includes a housing structure, an alloy, and a heating element. The housing structure includes an outer shell surrounding a cavity. The alloy is disposed of within the cavity. The alloy has a melting temperature range. The heating element is configured to transition the alloy from a solid state to a liquid state at a set temperature between the melting temperature range.

公开(公告)号：US20220143786A1

公开(公告)日：2022-05-12

申请号：US17572188

申请日：2022-01-10

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang ,  Anton J. deVilliers

IPC: B25B11/00 ,  H01L21/687 ,  H01L21/683

Abstract: An apparatus and method for uniformly holding a substrate without flexure or bending of the substrate, thereby enabling accurate shape measurements of the substrate such as wafer curvature, z-height values and other surface characteristics. Techniques include using a liquid as a supporting surface for a substrate thereby providing uniform support. Liquid used has a same specific gravity of a substrate being supported so that the substrate can float on the liquid without sinking. Uniform support of the substrate enables precision metrology.

公开(公告)号：US20210305060A1

公开(公告)日：2021-09-30

申请号：US17121546

申请日：2020-12-14

Applicant: Tokyo Electron Limited

Inventor： Anthony R. Schepis ,  Hoyoung Kang

IPC: H01L21/3213 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/321

Abstract: A method of processing a substrate includes forming a channel through a substrate, depositing a layer of polycrystalline silicon on sidewalls of the channel, and oxidizing uncovered surfaces of the polycrystalline silicon with an oxidation agent. The oxidizing agent causes formation of an oxidized layer, the oxidized layer having a uniform thickness on uncovered surfaces of the polycrystalline silicon. The method includes removing the oxidized layer from the channel with a removal agent, and repeating steps of oxidizing uncovered surfaces and removing the oxidized layer until removing a predetermined amount of the layer of polycrystalline silicon.

公开(公告)号：US10115726B2

公开(公告)日：2018-10-30

申请号：US15416916

申请日：2017-01-26

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang ,  Anton J. deVilliers

IPC: H01L21/311 ,  H01L27/108 ,  H01L21/308 ,  H01L21/027 ,  H01L21/8234

Abstract: Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.

公开(公告)号：US09508557B2

公开(公告)日：2016-11-29

申请号：US14676356

申请日：2015-04-01

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: H01L21/304 ,  H01L21/027 ,  H01L21/324 ,  H01L21/311 ,  H05B3/22 ,  H01L21/687 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/304 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/67109 ,  H01L21/67748 ,  H01L21/68735 ,  H05B3/22

Abstract: Provided is a method for processing a semiconductor substrate to reduce line roughness, the method comprising: positioning a substrate in a film-forming system, the film-forming system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrate so as to create a concave surface during processing; coating the substrate with a layer of material; performing a post apply bake process; flexing the substrate to create the concave surface either during the post apply bake or following the post apply bake process, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the layer of material on the substrate.

Abstract translation: 提供了一种处理半导体衬底以减少线粗糙度的方法，所述方法包括：将衬底定位在成膜系统中，所述成膜系统包括具有夹持机构的卡盘，所述夹持机构构造成将衬底保持在处理室中， 通过相对于衬底的周边移位衬底的中心来弯曲衬底，以便在加工过程中产生凹面; 用一层材料涂覆基材; 执行贴子烘焙过程; 在施加后烘烤或后施加烘烤过程期间使衬底弯曲以形成凹面，其中凹面具有在衬底的中心处测量的超过基数微米的凹度; 并且使衬底不折叠并且在衬底上的材料层中引起拉伸应力。

公开(公告)号：US20240194516A1

公开(公告)日：2024-06-13

申请号：US18581154

申请日：2024-02-19

Applicant: Tokyo Electron Limited

Inventor： Ronald Nasman ,  Gerrit J. Leusink ,  Rodney L. Robinson ,  Hoyoung Kang ,  Daniel Fulford

IPC: H01L21/687 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/505 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/68735 ,  C23C16/4409 ,  C23C16/4412 ,  C23C16/455 ,  C23C16/4585 ,  H01J37/32449 ,  C23C16/505 ,  H01L21/67069

Abstract: Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.

公开(公告)号：US20210132494A1

公开(公告)日：2021-05-06

申请号：US17145498

申请日：2021-01-11

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: G03F7/00

Abstract: Methods and systems for imprint lithography are described. In an embodiment, a method may include receiving a substrate in an imprint lithography chamber. Such a method may also include applying a deformable layer to a surface of the substrate. The method may further include injecting a gas that dissolves into the deformable layer more quickly than air into the chamber. Additionally, the method may include pressing a mold into the deformable layer. The method may also include controlling one or more processing parameters in order to achieve device formation objectives.

公开(公告)号：US10525416B2

公开(公告)日：2020-01-07

申请号：US15661551

申请日：2017-07-27

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang ,  Anton deVilliers ,  Corey Lemley

IPC: B01D19/00 ,  B01D65/02 ,  B01D71/36 ,  B01D71/56 ,  B01D63/14 ,  B01D63/06 ,  B01D29/01 ,  B01D29/11 ,  B01D65/00

Abstract: A process is disclosed for wetting a filter cartridge used to treat a liquid solvent used in semiconductor manufacture. In the process, a filter cartridge having void spaces wherein the void spaces contain residual gas from the manufacturing process used to make the filter cartridge is connected to a source of purging gas. The purging gas is flowed through the filter cartridge to at least partially displace at least a portion of the residual gas from the manufacturing process used to make the filter cartridge. Next, liquid solvent is pumped through the filter cartridge so that the purging gas dissolves into the liquid solvent and to at least partially fill the void spaces to thereby at least partially wet out the filter cartridge with the liquid solvent.

公开(公告)号：US20190027481A1

公开(公告)日：2019-01-24

申请号：US16137111

申请日：2018-09-20

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang ,  Anton J. deVilliers

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/027 ,  H01L21/8234

Abstract: Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.

公开(公告)号：US20180082833A1

公开(公告)日：2018-03-22

申请号：US15826091

申请日：2017-11-29

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: H01L21/02 ,  H01L21/027 ,  G03F7/20 ,  G03F7/26

CPC classification number: H01L21/02016 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/0274 ,  H01L21/67109 ,  H01L21/6715 ,  H01L21/67196 ,  H01L21/67207

Abstract: A processing chamber system includes a substrate mounting module configured to secure a substrate within a first processing chamber. The system also includes a first deposition module configured to apply a light-sensitive film to a front side surface of the substrate, and a second deposition module configured to apply a film layer to a backside surface of the substrate. The front side surface is opposite to the backside surface of the substrate. A substrate has a bare backside surface with a first coefficient of friction. A film layer is formed onto the backside surface of the substrate. The film layer formed on the backside surface of the substrate has a second coefficient of friction. The second coefficient of friction is lower than the first coefficient of friction.