公开(公告)号：US20190283206A1

公开(公告)日：2019-09-19

申请号：US16109665

申请日：2018-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiko KAWASAKI ,  Yukiteru MATSUI ,  Akifumi GAWASE

IPC: B24B37/26 ,  B24B37/24 ,  B24B53/017 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/321

Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.

公开(公告)号：US20180056482A1

公开(公告)日：2018-03-01

申请号：US15429542

申请日：2017-02-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiko KAWASAKI ,  Yukiteru MATSUI ,  Akifumi GAWASE

IPC: B24B53/017 ,  H01L21/306

CPC classification number: B24B53/017 ,  H01L21/30625

Abstract: According to one embodiment, a dresser includes a base metal plate, and a plurality of chip portions that are provided on the base metal plate. Each chip portion includes a Si substrate having a projection at an upper portion thereof and a diamond layer provided on the projection of the Si substrate.

公开(公告)号：US20210260719A1

公开(公告)日：2021-08-26

申请号：US17319637

申请日：2021-05-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiko KAWASAKI ,  Yukiteru MATSUI ,  Akifumi GAWASE

IPC: B24B37/26 ,  B24B37/24 ,  B24B53/017 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3105

Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.

公开(公告)号：US20200035636A1

公开(公告)日：2020-01-30

申请号：US16289644

申请日：2019-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiro KAWASAKI ,  Yukiteru MATSUI ,  Akifumi GAWASE

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4.

公开(公告)号：US20180277388A1

公开(公告)日：2018-09-27

申请号：US15992223

申请日：2018-05-30

Applicant: Toshiba Memory Corporation

Inventor： Yukiteru MATSUI ,  Kyoichi SUGURO ,  Akifumi GAWASE ,  Takahiko KAWASAKI

IPC: H01L21/3115 ,  H01L21/3215 ,  H01L21/3105 ,  H01J37/317 ,  H01L21/321 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L21/31155 ,  B81C2201/0123 ,  B81C2201/0125 ,  H01J37/3171 ,  H01J2237/31711 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/3215

Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.